AMS Verification Engineer

SpaceX

Confirmed live yesterday Low trust

Quick summary

Work type: On-site
Location: Redmond, WA
Salary: $125,000–$165,000 / yr
Posted: 64 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $193k

This role $145k

$113k $237k

below market most similar roles pay here above market

This role pays less than 92% of similar roles. Most pay $168,500–$217,987 — the blue band above. At the midpoint, this role pays about $145k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 851 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 590 roles with salary data.

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At a glance

TL;DR · AMS Verification Engineer

Role Posting Log in to save

The AMS Verification Engineer (RFIC Engineering) joins a cross-disciplinary team to develop next-generation RFICs for space and ground infrastructures. This role focuses on building and owning analog-on-top and digital-on-top design verification flows for full-chip simulations of in-house RFICs and RF-SoCs. Key responsibilities include developing testbenches for critical interfaces, creating behavioral models for RF, analog, and mixed-mode circuit blocks, and running EM/IR simulations. The engineer will collaborate with designers to improve simulation speed and accuracy for IPs like PLLs, DACs, and ADCs. Required technical skills include SystemVerilog, UVM, Python, and Verilog-A/AMS. The work addresses the technical challenge of enabling reliable connectivity in remote areas by expanding the performance and capabilities of the Starlink satellite network.

Skills

AMS Simulation System-Verilog UVM Python Verilog-A RFIC RF-SoC Mixed-Signal Gate-Level Simulation EM/IR Simulation RTL ASIC ATE Bandgap Baseband Amplifiers Mixers

What you'll do

Develop and own analog-on-top and digital-on-top design verification flows for full-chip simulations.
Develop testbenches and flows to simulate critical interfaces between RFICs and SoCs.
Improve simulation speed and accuracy for advanced mixed-signal IPs like PLLs, DACs, and ADCs.
Create behavioral models of RF, analog, and mixed-mode circuit blocks for chip verification.
Develop and prototype testplans in coordination with the ATE test engineering team.
Setup and run EM/IR simulations.

What we're looking for

Bachelor’s degree in an engineering discipline.
1+ years of research and/or industry experience in the field of integrated circuit design/verification.
Master’s degree or PhD in an engineering discipline with emphasis in integrated circuit design/verification (preferred).
Experience with AMS simulation tools and flows (preferred).
Experience with annotated gate-level simulation within an AMS simulator (preferred).
Experience in System-Verilog, UVM, and Python (preferred).
Experience in writing behavioral models for analog/mixed-mode IPs in Verilog-A/AMS (preferred).
U.S. citizenship, national, lawful permanent resident, refugee, asylee, or eligibility to obtain required Department of State authorizations.

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