AMS Verification Engineer

SpaceX

Confirmed live yesterday Trusted

Quick summary

Work type
On-site
Location
Irvine, CA
Salary
$125,000–$160,000 / yr
Posted
18 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $186k
This role $142k
$114k most similar roles pay here $230k

This role pays less than 88% of similar roles. Most pay $160,000–$212,500 — the shaded band above. At the midpoint, this role pays about $142k versus about $186k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 680 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 442 roles with salary data.

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At a glance

TL;DR · AMS Verification Engineer

AMS Verification Engineer (RFIC Engineering) will join cross-disciplinary teams to develop next-generation RFICs for space and ground infrastructure. The role focuses on creating "analog-on-top" and "digital-on-top" design verification flows for full-chip simulations of in-house RFICs and RF-SoCs. Key responsibilities include developing testbenches for critical interfaces, improving simulation speed and accuracy for mixed-signal IPs like PLLs, DACs, and ADCs, creating behavioral models for circuit blocks, and running EM/IR simulations. The candidate will collaborate with ATE test engineering teams to prototype testplans. Required skills include experience with AMS simulation tools, annotated gate-level simulation, SystemVerilog, UVM, and Python. Candidates should also possess knowledge of Verilog-A/AMS for behavioral modeling and a deep understanding of analog circuit fundamentals, including LDOs, bandgaps, and various amplifiers to solve complex connectivity challenges in the Starlink network.

What you'll do

  • Develop and own "analog-on-top" and "digital-on-top" design verification flows for full-chip simulations of RFICs and RF-SoCs.
  • Create testbenches and flows to simulate critical interfaces between integrated circuits and systems-on-chip.
  • Collaborate with designers to improve the speed and accuracy of simulations for advanced mixed-signal IPs like PLLs, DACs, and ADCs.
  • Develop behavioral models for RF, analog, and mixed-mode circuit blocks to be used in chip verification.
  • Partner with ATE test engineering teams to develop and prototype hardware testplans.
  • Set up and execute EM/IR simulations for integrated circuits.

What we're looking for

  • Bachelor's degree in an engineering discipline.
  • 1+ years of research and/or industry experience in integrated circuit design or verification.
  • Must be a U.S. citizen, national, lawful permanent resident, or eligible for required export control authorizations.
  • Master's degree or PhD in an engineering discipline with emphasis in IC design/verification (preferred).
  • Experience with AMS simulation tools, flows, and annotated gate-level simulation within an AMS simulator (preferred).
  • Experience in SystemVerilog, UVM, and Python (preferred).
  • Ability to write behavioral models for analog/mixed-mode IPs in Verilog-A/AMS (preferred).
  • Understanding of analog circuit fundamentals and digital circuit blocks (preferred).

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