Senior Verification Engineer | Microsoft Careers

Microsoft

Quick summary

Work type
On-site
Location
Redmond, WA
Salary
$119,800–$234,700 / yr
Posted
8 days ago
Closes
Nov 22, 2026

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $171k
This role $177k
$106k most similar roles pay here $248k

This role pays more than 72% of similar roles. Most pay $149,331–$191,687 — the shaded band above. At the midpoint, this role pays about $177k versus about $171k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 571 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 522 roles with salary data.

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At a glance

TL;DR · Senior Verification Engineer | Microsoft Careers

As a Senior Verification Engineer in the Compute Silicon and Manufacturing Engineering (CSME) team, you will play a pivotal role in ensuring the reliability and efficiency of Microsoft’s cloud hardware infrastructure. Your responsibilities include collaborating with architects and design engineers to develop comprehensive verification strategies and test plans for system-on-chip (SoC) designs, writing and debugging constrained random stimulus, scoreboards, and assertions, and developing UVM components to interface between test code and simulation environments. You will also define functional coverage metrics, debug failures, and mentor team members while fostering a collaborative environment that leverages industry-standard tools like System Verilog and C++. With expertise in SoC design verification, ARM architecture, and AI-based productivity tools, you will contribute to the continuous improvement of cloud infrastructure at scale.

What you'll do

  • Develop test plans covering verification strategy, requirements, and environments for system-on-chip (SOC) level verification.
  • Write and debug constrained random stimulus, scoreboards, checkers, and assertions to ensure design correctness.
  • Create Universal Verification Methodology (UVM) components interfacing between test code and simulation environments.
  • Define and implement functional coverage metrics to drive coverage closure in verification processes.
  • Mentor team members and collaborate on the reuse of verification components across teams.

What we're looking for

  • Doctorate in relevant field with 1+ year of experience or Master's with 4+ years, or Bachelor's with 5+ years.
  • 3+ years of experience in Computer Architecture and SoC design verification using System Verilog.
  • 3+ years developing and using UVM for verification environments.
  • Proven track record delivering complex SOC testbenches and simulation environments.
  • Experience with ARM architecture, AMBA protocols, and multiple product cycles from definition to Silicon.
  • Expertise in PCIe/CXL Controller/PHY IPs, I/O virtualization, or coherent fabric IPs and protocols.
  • Knowledge of full chip/system level flows and proficiency with AI-based verification tools.

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