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RTL Verilog SystemVerilog VHDL ASIC LPDDR HBM NoC CPU x86 ARM Cache Controller Memory Subsystem Digital Design Synthesis Timing Closure Physical Design Gate Level Simulation Power Analysis RTL Design Verification +15 more Show less

C++ SystemC HBM Memory_Hierarchies DRAM_Systems AI/ML GPU HPC Post_Silicon_Performance_Analysis SoC_Architecture TLM HBM2 HBM2E HBM3 +9 more Show less

SystemVerilog UVM C++ Python Perl Constrained-random testing Functional coverage Assertions CI/CD Debugging Performance profiling Memory subsystems Coherent interconnects GPU architecture Formal verification Emulation +11 more Show less

Python C++ UVM Verilog SystemVerilog VCS DVManager e Git CI/CD Linux +6 more Show less