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Active Keyword: SoC Design Remove filter Clear all

20 of up to 20 (filtered)

SoC Integration and Design Engineer

Broadcom

Mendota Heights, MN +2 1 day ago $109,700–$175,500
Actively hiring Confirmed live today Posted today High trust Below market
SoC Architecture SystemVerilog Verilog VHDL AMBA Synthesis Formal Verification CDC DFT Timing Closure Git JIRA DRAM SERDES UART Design Validation
8+ yrs exp
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SoC Design and Integration Engineer

Apple Inc

Austin, TX 3 days ago
Actively hiring Confirmed live yesterday Posted this week High trust
SoC Design Microarchitecture Logic Design Lint CDC Synthesis ECO Formal Verification STA Physical Design AMBA AXI AHB APB Asynchronous Interfaces
3+ yrs exp
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SoC Physical Design Engineer, PnR

Apple Inc

San Jose, CA 5 days ago $129,300–$225,300
Actively hiring Confirmed live today Posted this week High trust Below market
PnR Physical Design VLSI STA DRC LVS EMIR Redhawk Totem Voltus Verilog VHDL Python Perl TCL SPICE GDS2 Floor-planning Physical Synthesis
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Senior SOC Design Engineer

Nvidia

Santa Clara, CA 8 days ago $136,000–$218,500
Actively hiring Confirmed live today High trust Competitive pay
SOC Design RTL Design ASIC Design Physical Design DFT EDA Tools Python Perl Synthesis Padring SOC Integration Design Automation Front-end Chip Implementation
3+ yrs exp Hybrid
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Wireless SoC Design Engineer

Apple Inc

Waltham, MA 10 days ago $165,800–$292,400
Actively hiring Confirmed live today Trusted Competitive pay
SystemVerilog Verilog ASIC Design RTL Design SoC Architecture AXI AHB UPF Low-Power Design LINT CDC RDC EDA Tools Micro-architecture Digital Design
10+ yrs exp
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Wireless SoC Design Engineer

Apple Inc

Sunnyvale, CA 10 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Trusted Above market
SystemVerilog Verilog ASIC Design Flow RTL Design SoC Architecture AXI AHB UPF Low-Power Design LINT CDC RDC EDA Tools Micro-architecture Specification Digital Design
10+ yrs exp
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Wireless SoC Design Engineer

Apple Inc

San Diego, CA 10 days ago $175,000–$308,500
Actively hiring Confirmed live today Trusted Above market
SystemVerilog Verilog ASIC Design RTL Design SoC Architecture AXI AHB UPF Low-Power Design LINT CDC RDC EDA Tools Micro-architecture Digital Design
10+ yrs exp
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Wireless SoC Design Engineer

Apple Inc

Irvine, CA 10 days ago $175,000–$308,500
Actively hiring Confirmed live yesterday Trusted Above market
SystemVerilog Verilog ASIC Design RTL Design SoC Architecture AXI AHB UPF Low-Power Design LINT CDC RDC EDA Tools Micro-architecture Digital Design
10+ yrs exp
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Wireless SoC Design Engineer

Apple Inc

Sunnyvale, CA 10 days ago $129,300–$225,300
Actively hiring Confirmed live today Trusted Competitive pay
SystemVerilog Verilog ASIC Design Flow RTL Design SoC Architecture AXI AHB UPF Low-Power Design LINT CDC RDC EDA Tools Micro-architecture Specification Digital Design
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Wireless SoC Design Engineer

Apple Inc

San Diego, CA 10 days ago $122,700–$214,300
Actively hiring Confirmed live today Trusted Below market
SystemVerilog Verilog ASIC Design Flow RTL Design SoC Architecture AXI AHB UPF Low-Power Design LINT CDC RDC EDA Tools Micro-architecture Specification Digital Design
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Wireless SoC Design Engineer

Apple Inc

Irvine, CA 10 days ago $122,700–$214,300
Actively hiring Confirmed live yesterday Trusted Below market
SystemVerilog Verilog ASIC Design Flow RTL Design SoC Architecture AXI AHB UPF Low-Power Design LINT CDC RDC EDA Tools Micro-architecture Specification Digital Design
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SOC Design Verification Engineer

Apple Inc

Sunnyvale, CA 11 days ago $129,300–$225,300
Actively hiring Confirmed live today Trusted Competitive pay
SystemVerilog UVM Verilog UPF Python C C++ Formal Verification JasperGold PCIe AXI AHB SVA ASIC SOC Perl Assembly
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SOC Design Verification Engineer

Apple Inc

San Diego, CA 11 days ago $122,700–$214,300
Actively hiring Confirmed live yesterday Trusted Below market
SystemVerilog UVM Verilog UPF Python C C++ Formal Verification JasperGold PCIe AXI AHB SVA RTL ASIC SOC WiFi Bluetooth Perl
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SOC Design Verification Engineer

Apple Inc

Irvine, CA 11 days ago $122,700–$214,300
Actively hiring Confirmed live yesterday Trusted Below market
SystemVerilog UVM Verilog UPF Python C++ Perl Formal Verification JasperGold SVA PCIe AXI AHB WiFi Bluetooth RTL Verification AI/ML
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SOC Design Verification Engineer

Apple Inc

Sunnyvale, CA 11 days ago $184,700–$324,800
Actively hiring Confirmed live today Trusted Above market
SystemVerilog UVM Verilog UPF Python C C++ Formal Verification JasperGold PCIe AXI AHB SVA Perl RTL ASIC SOC WiFi Bluetooth
10+ yrs exp
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SOC Design Verification Engineer

Apple Inc

San Diego, CA 11 days ago $175,000–$308,500
Actively hiring Confirmed live today Trusted Above market
SystemVerilog UVM Verilog UPF Python C++ Perl Formal Verification JasperGold SVA PCIe AXI AHB WiFi Bluetooth RTL Verification AI/ML Assembly
10+ yrs exp
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SOC Design Verification Engineer

Apple Inc

Irvine, CA 11 days ago $175,000–$308,500
Actively hiring Confirmed live today Trusted Above market
SystemVerilog UVM Verilog UPF Python C++ Perl Formal Verification JasperGold SVA ASIC SOC PCIe AXI AHB WiFi Bluetooth AI/ML
10+ yrs exp
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SOC Design Verification Engineer

Qualcomm

San Diego, CA 20 days ago $101,400–$152,200
Actively hiring Confirmed live today Trusted Below market
ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Design Verification Scripting Logic Design
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Senior EDA Engineer, SOC Design Methodology

Nvidia

Santa Clara, CA 20 days ago
Actively hiring Confirmed live today Trusted
ASIC Design SoC Design Verilog SystemVerilog C++ Python Perl Tcl Synopsys Fusion Compiler Data Structures Algorithms Build Infrastructure RTL Agentic AI Claude Code Cursor
3+ yrs exp Hybrid
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SoC Machine Learning Design Engineer

Apple Inc

Cupertino, CA 21 days ago $184,700–$324,800
Actively hiring Confirmed live today Trusted Above market
Machine Learning Generative AI PyTorch TensorFlow JAX MLX Verilog SystemVerilog VHDL UVM RAG Deep Neural Networks Reinforcement Learning Static Timing Analysis CDC RDC Data Structures Algorithms
10+ yrs exp
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