Wireless SoC Design Engineer

Apple Inc

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Quick summary

Work type
On-site
Location
Waltham, MA
Salary
$165,800–$292,400 / yr
Posted
10 days ago
Freshness
Confirmed live today

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Competitive pay

How this pay compares to similar roles

Similar $205k
This role $229k
$133k $309k
below market most similar roles pay here above market

This role pays more than 64% of similar roles. Most pay $168,500–$241,750 — the blue band above. At the midpoint, this role pays about $229k versus about $205k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · Wireless SoC Design Engineer

The Wireless SoC Design Engineer joins the wireless silicon development team to design CPU-based subsystems for high-performance, low-power wireless SoCs. This role involves writing micro-architecture and design specifications, coding RTL in SystemVerilog, and integrating industry-standard and custom hardware IPs. Key responsibilities include optimizing memories and hard macros, supporting multi-level verification efforts, and performing analysis on area, timing, and power. The engineer must utilize industry-standard static tools for LINT, CDC, and RDC checks while collaborating with software, firmware, and platform engineering teams on hardware/software/power partitioning. Required skills include knowledge of digital design, SoC architecture, Verilog, and ASIC design flows. The work focuses on developing energy-efficient silicon and meeting specific power, performance, and area goals for wireless products.

What you'll do

  • Write micro-architecture and design specifications for CPU-based subsystems.
  • Code RTL designs in SystemVerilog following established design guidelines.
  • Integrate hardware IP blocks and optimize required memories and hard macros.
  • Support verification efforts across multiple levels of the design process.
  • Perform design checks using industry standard static tools like LINT, CDC, and RDC.
  • Analyze and optimize design area, timing, and power metrics.
  • Participate in hardware, software, and power partitioning discussions with engineering teams.

What we're looking for

  • BS degree with 10+ years of relevant experience.
  • Familiarity with the ASIC design flow.
  • Knowledge of digital design, SoC architecture, and HDL languages like Verilog.
  • Experience writing micro-architecture specifications and converting them to design (preferred).
  • Exposure to design methodologies and industry standard EDA tools (preferred).
  • Experience with AXI/AHB bus fabric and processor sub-systems (preferred).
  • Understanding of UPF and low-power design and implementation techniques (preferred).
  • Self-starter and willingness to learn (preferred).

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