Wireless SoC Design Engineer

Apple Inc

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Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$122,700–$214,300 / yr
Posted
10 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $205k
This role $168k
$106k $280k
below market most similar roles pay here above market

This role pays less than 72% of similar roles. Most pay $168,500–$241,750 — the blue band above. At the midpoint, this role pays about $168k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · Wireless SoC Design Engineer

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The Wireless SoC Design Engineer joins the wireless silicon development team to design CPU-based subsystems for high-performance, low-power wireless SoCs. Working closely with SoC architects and IP developers, the engineer develops SoCs that meet specific power, performance, and area goals for Apple devices. Key responsibilities include writing micro-architecture and design specifications, coding RTL in SystemVerilog, and integrating industry-standard and custom hardware IPs. The role involves optimizing memories and hard macros, supporting multi-level verification, and utilizing static tools for LINT, CDC, and RDC checks. Candidates must possess knowledge of digital design, SoC architecture, and HDL languages like Verilog. The position focuses on hardware/software/power partitioning and low-power design techniques, specifically addressing the technical challenges of developing energy-efficient wireless silicon for leading-edge products.

Skills

SystemVerilog Verilog ASIC Design Flow RTL Design SoC Architecture AXI AHB UPF Low-Power Design LINT CDC RDC EDA Tools Micro-architecture Specification Digital Design

What you'll do

  • Write micro-architecture and design specifications for CPU-based subsystems.
  • Code RTL designs in SystemVerilog following established design guidelines.
  • Integrate hardware IP blocks and optimize memories and hard macros.
  • Support verification efforts at multiple levels of the design process.
  • Perform design checks using industry standard static tools like LINT, CDC, and RDC.
  • Analyze and optimize area, timing, and power metrics for wireless SoCs.
  • Participate in hardware, software, and power partitioning discussions with engineering teams.

What we're looking for

  • Minimum requirement of a bachelor's degree.
  • Familiarity with the ASIC design flow.
  • Knowledge of digital design, SoC architecture, and HDL languages like Verilog.
  • MSEE with some years of industry experience (preferred).
  • Experience writing micro-architecture specifications and converting them to design (preferred).
  • Exposure to design methodologies and industry standard EDA tools (preferred).
  • Experience with AXI/AHB bus fabric and processor sub-systems (preferred).
  • Understanding of UPF and low-power design & implementation techniques (preferred).

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