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UVM OVM SystemVerilog Assertions (SVA) Verilog VHDL Python TCL Perl Mixed-Signal Verification Logic Synthesis Static Timing Analysis Formal Verification Place and Route EDA Tools CMOS Bipolar Scripting +12 more Show less

FPGA RTL VHDL Verilog SystemVerilog SoC Python Tcl Linux Git CI/CD Xilinx Ethernet PCIe JESD204 SPI I2C UART CAN MIL-STD-1553 +15 more Show less

VLSI RTL Design micro architecture Synthesis Silicon Engineering Power Control Systems ASIC +2 more Show less

High-speed Digital Design Baseband Design Signal Integrity Analysis Simulation Power Management ICs RF Debug PWB Layout BOM Capture Firmware Development Integration +5 more Show less

High-Speed I/O PHY IP SoC AXI CHI CXS.B CXL PCIe UA-Link Signal Integrity Power Integrity Mixed-Signal Design Digital Design Chiplet Silicon Design +10 more Show less

RTL ASIC FPGA Synthesis Static Timing Analysis Clock Domain Crossing CDC Bus Fabric Formal Verification Simulation JIRA FinFET TSMC GlobalFoundries Samsung EDA Tools Microarchitecture Power Analysis +13 more Show less

Verilog System Verilog RTL UVM SerDes Ethernet InfiniBand PCIe USB Silicon Photonics Static Timing Analysis Synthesis Firmware Co-Packaged Optics CDR DFE CTLE +12 more Show less

RTL ASIC Design NVLink PCI-Express Ethernet UCIe System-on-Chip Network-on-Chip Micro-architecture Synthesis Formal Verification SoC Integration High-speed Connectivity +8 more Show less

SystemVerilog UVM VMM SerDes PCI Express USB SATA Python Perl C/C++ Assertion-based Verification Functional Coverage coverage driven verification Mixed-signal Design Simulation Debug +11 more Show less