Senior Digital VLSI Design Engineer

Broadcom

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Quick summary

Work type
On-site
Location
Fort Collins, COSan Jose, CA
Employment
Full-time
Posted
81 days ago
Freshness
Confirmed live today

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How this pay compares to similar roles

Similar $194k
$140k most similar roles pay here $245k

This listing doesn't post a salary. Most similar roles pay $172,000–$216,739.

Based on 240 similar postings.

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About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 223 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 160 roles with salary data.

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At a glance

TL;DR · Senior Digital VLSI Design Engineer

As a Senior Digital VLSI Design Engineer, you will serve as the technical authority responsible for defining and enforcing synchronization strategies across complex, multi-clock domains in advanced process nodes. You will manage the constraint creation process for synthesis, establish full-chip CDC/RDC methodologies, and ensure zero-defect silicon through rigorous constraints and waivers. Collaborating with Architecture and Chip Lead teams, you will review testability, DFT design, clocking, and reset architectures to identify metastability or reset-glitch issues before RTL freeze. You will utilize industry-standard tools including SpyGlass CDC/RDC, Spyglass Lint, JasperGold, or Meridian. The role involves managing high-speed interfaces such as SerDes, LPDDR5/6, DDR4/5, and HBM where asynchronous boundaries are critical. Additionally, you will mentor the broader design team on synthesis, DFT, and CDC/RDC best practices while driving automated flows for multi-site global teams.

What you'll do

  • Define and enforce synchronization strategies across complex, multi-clock domains in advanced process nodes.
  • Own the constraint creation process for synthesis and full-chip CDC/RDC methodology.
  • Establish rigorous constraints and waivers to ensure zero-defect silicon.
  • Review testability, DFT design, clocking, and reset architectures early in the design cycle.
  • Identify potential metastability or reset-glitch issues before RTL freeze.
  • Perform structural and functional verification of crossings using industry-standard tools like SpyGlass or JasperGold.
  • Mentor the broader design team on Synthesis, DFT, and CDC/RDC best practices.
  • Develop automated flows to streamline sign-off for multi-site global teams.

What we're looking for

  • Bachelor of Science in Electrical Engineering is required.
  • Master's degree or PhD in Electrical Engineering is preferred.
  • 8+ years of related experience are required.
  • Expertise in Synthesis, DFT, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) sign-off for high-speed complex IPs is required.
  • Mastery of structural and functional verification of crossings using tools like SpyGlass CDC/RDC, Spyglass Lint, JasperGold, or Meridian is required.
  • Experience with high-speed interfaces such as SerDes, LPDDR5/6, DDR4/5, or HBM is highly desired.

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