Senior Digital Design Engineer, Air Dominance and Strike

Anduril Industries

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Work type
On-site
Location
Costa Mesa, CA
Salary
$166,000–$220,000 / yr
Posted
55 days ago
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Confirmed live today

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How this pay compares to similar roles

Similar $190k
This role $193k
$142k $228k
below market most similar roles pay here above market

This role pays more than 64% of similar roles. Most pay $164,435–$216,250 — the blue band above. At the midpoint, this role pays about $193k versus about $190k for comparable roles.

Based on 240 similar postings.

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About Anduril Industries

Anduril Industries is a defense technology company that builds advanced hardware and software systems for national security, including autonomous drones, surveillance systems, and the Lattice AI command platform.

Anduril Industries currently has 901 open roles on FindRole.

Listed pay typically runs $166,000–$220,000 across 858 roles with salary data.

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At a glance

TL;DR · Senior Digital Design Engineer, Air Dominance and Strike

JOB TITLE: Senior Digital Design Engineer, Air Dominance and Strike The Senior Digital Design Engineer joins the Air Dominance and Strike Electrical Engineering Team to develop high-reliability avionics, embedded processing, and power systems for Group 5 air vehicles and missile platforms. This role involves designing and integrating RTL for FPGA and SoC platforms used in high-performance embedded systems and mission-critical hardware. Key responsibilities include translating hardware requirements into microarchitecture, implementing RTL in VHDL, Verilog, or SystemVerilog, and managing simulation, synthesis, and timing closure. The engineer will perform lab bring-up, debug functional issues, and support system integration. Required skills include proficiency in Linux-based environments, Git workflows, and Tcl or Python scripting. The work addresses the technical challenge of delivering flight-critical electronics and FPGA-based processing architectures for next-generation autonomous air platforms.

What you'll do

  • Design and implement RTL in VHDL, Verilog, or SystemVerilog for FPGA and SoC-based systems.
  • Translate system and hardware requirements into microarchitecture, interface definitions, and implementation plans.
  • Own FPGA designs or major functional blocks from architecture through integration, timing closure, and lab debug.
  • Develop and execute simulation, synthesis, and implementation flows, including timing and resource closure.
  • Debug functional, timing, and integration issues in simulation and on hardware.
  • Support board bring-up, lab validation, and system integration on target platforms.
  • Contribute to reusable design practices, coding standards, and development workflows.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
  • 8+ years of FPGA, ASIC, or closely related digital design experience.
  • Proficiency in VHDL and/or Verilog/SystemVerilog.
  • Hands-on experience with simulation, synthesis, implementation, and timing closure on modern FPGA platforms.
  • Hands-on debug experience in simulation and on hardware.
  • Strong digital design fundamentals including clocking, resets, state machines, CDC awareness, and interface design.
  • Proficiency with Linux-based development environments, Git-based workflows, and Tcl and/or Python scripting.
  • Eligible to obtain and maintain an active U.S. Secret security clearance.

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