Senior HSIO Digital Design Engineer

Samsung Semiconductor

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$138,000–$206,000 / yr
Posted
43 days ago
Freshness
Confirmed live 2 days ago

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $193k
This role $172k
$128k most similar roles pay here $236k

This role pays less than 68% of similar roles. Most pay $169,250–$216,250 — the shaded band above. At the midpoint, this role pays about $172k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Samsung Semiconductor

Samsung Semiconductor is the global semiconductor business unit of Samsung Electronics, designing and manufacturing memory chips, logic semiconductors, and foundry solutions for a broad range of applications.

Samsung Semiconductor currently has 49 open roles on FindRole.

Listed pay typically runs $163,000–$253,000 across 49 roles with salary data.

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At a glance

TL;DR · Senior HSIO Digital Design Engineer

The Senior HSIO Digital Design Engineer joins the Location Group to develop next-generation high-speed I/O designs for AI production platforms. This role involves developing High-Speed I/O PHY IP, focusing on die-to-die chiplet interfaces and similar technologies. The engineer will manage the end-to-end digital design flow while collaborating with system and analog teams to navigate trade-offs between high-speed serial interconnect protocols and mixed-signal design impacts. Key technical requirements include expertise in Signal Integrity and Power Integrity modeling for High-Speed I/O designs, as well as familiarity with HSIO PHY layers, architectures, and SoC protocols such as AXI, CHI, CXS.B, CXL, PCIe, and UA-Link. The position addresses the critical challenge of creating highly integrated products by optimizing high-speed communication within complex systems to support advanced mobile, wearable, and infrastructure applications.

What you'll do

  • Develop high-speed I/O (HSIO) designs for AI production platforms and chiplet interfaces.
  • Design and develop High-Speed I/O PHY IP.
  • Manage the end-to-end digital design flow from concept to productization.
  • Evaluate trade-offs for high-speed serial interconnect protocols.
  • Integrate analog and mixed-signal design requirements into digital-on-top development flows.
  • Perform Signal Integrity (SI) and Power Integrity (PI) modeling for High-Speed I/O designs.
  • Implement SoC protocols including AXI, CHI, CXS, CXL, PCIe, and UA-Link.

What we're looking for

  • Candidates must have a BS in Electrical Engineering with 5+ years of experience, an MS with 3+ years, or a PhD.
  • Candidates must have at least 3 years of industry experience in digital design for die-to-die interfaces or similar high-speed I/O technologies.
  • Candidates must have hands-on experience in High-Speed I/O PHY IP development.
  • Candidates must have a strong understanding of high-speed serial interconnect protocols and associated design trade-offs.
  • Candidates must understand how analog and mixed-signal design and verification impact digital-on-top development flows.
  • Candidates must possess knowledge of Signal Integrity (SI) and Power Integrity (PI) modeling for High-Speed I/O designs.
  • Candidates must have an understanding of SoC protocols including AXI, CHI, CXS.B/C, CXL, PCIe, and UA-Link.
  • Candidates must be familiar with HSIO PHY layers protocols and architectures.

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