below marketmost similar roles pay hereabove market
This role pays less than
70%
of similar roles. Most pay
$165,825–$216,250
— the blue band above.
At the midpoint, this role pays about
$172k
versus about
$191k
for comparable roles.
Based on 240 similar postings.
Employer
About Samsung Semiconductor
Samsung Semiconductor is the global semiconductor business unit of Samsung Electronics, designing and manufacturing memory chips, logic semiconductors, and foundry solutions for a broad range of applications.
Samsung Semiconductor currently has
36 open roles
on FindRole.
Listed pay typically runs
$163,000–$253,000
across 36 roles with salary data.
The Senior HSIO Digital Design Engineer joins the San Jose Location Group to develop next-generation High-Speed I/O for AI production platforms. Working within the broader SoC organization, this role involves building products from initial algorithm design and architecture definition through to silicon design, platform integration, and performance optimization. The engineer will focus on die-to-die chiplet interfaces and high-speed serial interconnect protocols, ensuring seamless collaboration with system and analog teams. Key responsibilities include managing digital-on-top development flows, Signal Integrity modeling, and Power Integrity modeling. Required technical expertise includes proficiency with HSIO PHY layers and SoC protocols such as AXI, CHI, CXS.B, CXL, PCIE, and UA-Link. The role solves critical high-speed connectivity challenges for mobile and wearable applications within a highly integrated SoC environment.
Develop High-Speed I/O (HSIO) PHY IP for AI production platforms.
Design digital interfaces for die-to-die (chiplet) and other high-speed technologies.
Manage the end-to-end digital design flow from concept to productization.
Perform Signal Integrity (SI) and Power Integrity (PI) modeling for HSIO designs.
Implement high-speed serial interconnect protocols and evaluate associated design trade-offs.
Integrate analog and mixed-signal design impacts into digital-on-top development flows.
Support the development of next-generation location technology for mobile and wearable applications.
What we're looking for
BS in Electrical Engineering with 5+ years of experience, MS in Electrical Engineering with 3+ years of experience, or a PhD in Electrical Engineering.
3+ years of industry experience specializing in digital design for die-to-die (chiplet) interfaces or similar high-speed I/O technologies.
Hands-on experience in High-Speed I/O PHY IP development.
Strong understanding of high-speed serial interconnect protocols and associated design trade-offs.
Solid understanding of how analog and mixed-signal design and verification impact digital-on-top development flows.
Knowledge of Signal Integrity (SI) and Power Integrity (PI) modeling for High-Speed I/O designs.
Understanding of SoC protocols including AXI/CHI/CXS.B/CXL/PCIE/UA-Link (preferred).
Familiarity with HSIO PHY layers protocols and architectures (preferred).