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PCIe UVM System Verilog Verilog NVMe RDMA SoC Digital Design Computer Architecture Verification IP Tapeout Data Link Layer +7 more Show less

Physical Verification DRC LVS ERC Antenna Calibre Python TCL Perl Shell Ansible Linux Azure EntraID PDK CAD Flow Automation IC Design +12 more Show less

System Verilog UVM Verilog VHDL C C++ Python Ruby Perl Makefiles Agile FPGA Emulation Firmware Hardware Design Silicon Verification Functional Coverage Assertion Scripting +14 more Show less

Questa VCS Jasper Gold Verdi Python Perl SoC DFT JTAG TAP UPF RTL Scripting Functional Verification +9 more Show less

Python Ruby C ASIC Linux TCP/IP BGP OSPF LACP VXLAN Docker Kubernetes CI/CD Wireshark Spirent TestCenter Avalanche Ixia Breaking Point +13 more Show less

ASIC FPGA UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models +9 more Show less

ASIC FPGA UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models +9 more Show less

ASIC FPGA UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models +9 more Show less

ASIC FPGA UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models +9 more Show less

UVM SystemVerilog OVM AMS RTL SoC Python MATLAB C C++ Ruby Perl Azure DFT Simulation Verification Methodology Scripting Data Analysis AI Tools +14 more Show less