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Analog Mixed Signal/Power Management Design Engineer

Qualcomm

San Diego, CA 16 days ago $142,400$213,600
Actively hiring Verified listing Competitive pay
Cadence MATLAB SPICE Verilog VHDL CMOS FinFET ASIC BCD Python C++ SystemVerilog AMS PLL DataConverters ClassDAudioAmplifier BuckBoostSwitchingRegulators ChargePumps PrecisionReferences SensorSignalAcquisitionCircuit AudioAmplifiers

Analog/Mixed-Signal IC design Engineer

Qualcomm

San Diego, CA 25 days ago $142,400$213,600
Actively hiring Competitive pay
Cadence ADE MATLAB SPICE Verilog VHDL Python PostgreSQL Kubernetes AWS Terraform CI/CD Git JIRA Confluence Prometheus Grafana

Mixed Signal Design / Systems Engineer

Qualcomm

Santa Clara, CA 50 days ago $198,600$297,800
Actively hiring Above market
Python Verilog VHDL MATLAB SPICE CADENCE CMOS TFT LTPS ASIC Sensor Physics HW/SW Co-optimization Firmware Development System Modeling Circuit Specifications Simulation Tools Algorithm Development Performance Optimization Layout Design Manufacturability Reliability

Senior Mixed Signal Design Engineer

Nvidia

Santa Clara, CA 80 days ago $136,000$218,500
Actively hiring Competitive pay
SystemVerilog Verilog Perl Python SATA PCIe USB DFE CTLE CDR FPGA

Mixed Signal Design Validation Engineer

Nvidia

Santa Clara, CA 88 days ago $168,000$264,500
Actively hiring Above market
Python Git MATLAB JMP SerDes measurement_theory test_instruments optical_transceivers

Mixed Signal Design Validation Engineer

Nvidia

Santa Clara, CA 88 days ago $116,000$189,750
Actively hiring Below market
Python Git MATLAB JMP SerDes measurement_theory test_instruments optical_transceivers

Manager, Digital Design - Mixed-Signal High-Speed I/O SerDes

Nvidia

Santa Clara, CA 147 days ago $196,000$310,500
Actively hiring Above market
Verilog SystemVerilog UVM RTL PCIe Ethernet Custom digital circuit design FFE DFE CTLE CDR offset cancellation Static timing analysis Formal verification tools High-speed SerDes I/O Mixed-signal chip design Mentorship Team leadership Communication skills