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UVM OVM SystemVerilog Assertions (SVA) Verilog VHDL Python TCL Perl Mixed-Signal Verification Logic Synthesis Static Timing Analysis Formal Verification Place and Route EDA Tools CMOS Bipolar Scripting +12 more Show less

HFSS ADS Cadence Allegro EM Simulation SI/PI Package Design High-Density Interconnects Quantum Computing CMOS Communication Theory +5 more Show less

CMOS Mixed Signal Design Cadence ADE MATLAB SPICE Verilog VHDL PLL SERDES 5G Analog Design Automation Layout Silicon Evaluation +8 more Show less

SystemVerilog UVM SVA VCS Questa JasperGold Python Perl Gate Level Simulation Formal Verification mixed signal simulation PCIe USB MIPI CXL LPDDR5 LPDDR6 Low Power Verification +13 more Show less

Cadence Virtuoso ASIC Design SerDes DDR PLL DAC ADC Python MATLAB SPICE Verilog VHDL Circuit Simulation Schematic Capture FinFET CMOS +11 more Show less

RTL ASIC Design Mixed-Signal IP Digital Signal Processing VCS Fusion Compiler PrimeTime Power Compiler Spyglass DFT STA CDC Python Perl GDSII Synthesis Formal Verification Floorplanning Pre-silicon Simulation +14 more Show less

Mixed-Signal IC Design CMOS FinFET Cadence SPICE MATLAB Verilog VHDL ASIC Layout Data Converters PLL Analog Design Automation ATE Verification +10 more Show less

Cadence Virtuoso ASIC Design SerDes PLL DAC ADC Matlab Python SPICE Verilog VHDL CMOS FinFET Signal Processing Schematic Capture +10 more Show less

SystemVerilog Verilog Mixed-Signal Design SerDes PLL ADC CTLE CDR DFE Python Perl FPGA SATA PCIe USB Circuit Modeling Scripting Silicon Bringup ATE +14 more Show less