Manager, Digital Design, Mixed-Signal High-Speed I/O SerDes

Nvidia

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $196,000–$310,500 / yr
Employment: Full-time
Posted: 5 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $210k

This role $253k

$150k $328k

below market most similar roles pay here above market

This role pays more than 84% of similar roles. Most pay $177,250–$243,500 — the blue band above. At the midpoint, this role pays about $253k versus about $210k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1763 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1151 roles with salary data.

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At a glance

TL;DR · Manager, Digital Design, Mixed-Signal High-Speed I/O SerDes

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As a Senior Digital Design Manager in the Mixed-Signal High-Speed I/O SerDes group, you will lead and mentor a team of engineers developing mixed-signal chips. Your daily responsibilities include supervising algorithm specifications, evaluating PPA trade-offs, and guiding the design of digital circuits like filters and analog calibration circuits. You will lead front-end design flows including Lint, CDC, Synthesis, DFT, LEC, and STA while coordinating with back-end teams for chip tape-outs. You must utilize Verilog, SystemVerilog, and UVM while applying expertise in logic design, circuit modeling, and adaptation algorithms such as FFE, DFE, CTLE, CDR, and offset cancellation. This role focuses on high-speed SerDes I/O digital design for standard and proprietary protocols like Ethernet and PCIe within sophisticated SoCs.

Skills

Verilog SystemVerilog Mixed-Signal Design RTL UVM Lint CDC Synthesis DFT LEC STA PCIe Ethernet SerDes Logic Design Circuit Modeling Formal Verification

What you'll do

Lead and mentor a team of engineers in developing mixed-signal chips.
Supervise the planning and specification of algorithms while evaluating PPA trade-offs.
Guide the design of digital circuits such as filters and analog calibration circuits.
Oversee verification of digital designs using direct and random testing methodologies.
Lead front-end design flows including Lint, CDC, Synthesis, DFT, LEC, and STA.
Drive silicon bring-up efforts and performance optimization.
Establish and maintain standard methodologies for mixed-signal design and verification.

What we're looking for

M.S. or Ph.D. in Electrical Engineering or equivalent experience.
Over 8 years of overall experience in mixed signal.
Proven experience in mixed-signal chip design with 3+ years in a leadership role.
Expertise in Verilog or SystemVerilog, logic design, and circuit modeling in RTL for mixed-signal blocks.
Strong background in custom digital circuit design and adaptation algorithms including FFE, DFE, CTLE, CDR, and offset cancellation.
Knowledge of high-speed SerDes I/O digital design and protocols like Ethernet and PCIe.
Experience with industry-standard verification methodologies such as UVM.
Proficiency with static timing and formal verification tools.