Manager, Digital Design - Mixed-Signal High-Speed I/O SerDes

Nvidia

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $196,000–$310,500 / yr
Posted: 146 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $190k

This role $253k

$133k most similar roles pay here $329k

This role pays more than 90% of similar roles. Most pay $159,600–$221,225 — the shaded band above. At the midpoint, this role pays about $253k versus about $190k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 855 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 843 roles with salary data.

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At a glance

TL;DR · Manager, Digital Design - Mixed-Signal High-Speed I/O SerDes

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As a Senior Digital Design Manager in NVIDIA’s Mixed-Signal High-Speed I/O SerDes group, you will lead a team of engineers developing cutting-edge technology for gaming, AI, deep learning, and autonomous driving applications. Your daily responsibilities include mentoring your team to develop mixed-signal chips, overseeing the planning and evaluation of PPA trade-offs, guiding digital circuit design, ensuring verification through direct and random testing methodologies, leading front-end design flows, coordinating with back-end teams for successful tape-outs, and collaborating across multi-functional teams to align technology roadmaps. You will need an M.S. or Ph.D. in Electrical Engineering, over 8 years of experience in mixed-signal chip design, expertise in Verilog/SystemVerilog, custom digital circuit design, high-speed SerDes I/O digital design, UVM verification methodologies, and static timing/formal verification tools, along with strong leadership and communication skills.

Skills

Verilog SystemVerilog UVM RTL PCIe Ethernet Custom digital circuit design FFE DFE CTLE CDR offset cancellation Static timing analysis Formal verification tools High-speed SerDes I/O Mixed-signal chip design Mentorship Team leadership Communication skills

What you'll do

Lead and mentor a team of engineers in developing mixed-signal chips.
Supervise planning and evaluation of PPA trade-offs for algorithms.
Guide the design of digital circuits including filters and analog calibration.
Ensure verification of digital designs using direct and random testing methods.
Coordinate front-end design flows with back-end teams for chip tape-outs.

What we're looking for

M.S. or Ph.D. in Electrical Engineering and over 8 years of experience in mixed-signal chip design.
Proven leadership in a mixed-signal team with expertise in Verilog/SystemVerilog for RTL modeling.
Deep understanding of high-speed SerDes I/O digital design, including FFE, DFE, CTLE, CDR, and offset cancellation algorithms.
Experience with UVM and static timing/formal verification tools for digital circuit verification.
Strong background in custom digital circuit design and PPA trade-off evaluations.
Excellent communication and leadership skills to drive technical strategy and align technology roadmaps.

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