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SystemVerilog UVM OVM Python C++ Verilog VHDL SystemC Perl Linux Makefiles Formal Verification Generative AI 3GPP DSP RTL Design +11 more Show less

Python .NET Object-Oriented Programming UI Automation SDLC Azure DevOps TFS Defect Tracking Medical Device Testing Verification and Validation Software Testing +6 more Show less

Python Matlab C/C++ LabVIEW Spectrum Analyzers Network Analyzers Vector Signal Generators Oscilloscopes CAD Link Budget Analysis Signal Chain Characterization Test Automation CI/CD Source Control DFT DFM +11 more Show less

Verilog system Verilog UVM Python C++ Perl C Shell MySQL PHP Linux Unix Windows HDL Simulation Debugging Oscilloscopes Logic Analyzers +13 more Show less

Verilog system Verilog UVM Python C++ C Perl Shell MySQL PHP Linux Unix Windows HDL Digital Systems Computer Organization Hardware Design Simulation Debugging Oscilloscopes +15 more Show less

Verilog system Verilog UVM Python C++ C Perl Shell MySQL PHP Linux Unix Windows HDL Logic Design Simulation Debugging Oscilloscopes Logic Analyzers +14 more Show less

MIL-STD-810 MIL-STD-461 MIL-STD-464 MIL-STD-704 DO-160 Requirements Management Jama DOORS Polarion Confluence Excel V-Model Systems Engineering Hardware Qualification Verification Cross-Reference Matrices AS9100 +11 more Show less

SystemVerilog UVM C C++ Verilog VHDL Python Perl Emulation Power Estimation SpeedBridges DPI Transactors Coverage +8 more Show less

MIL-STD-810 MIL-STD-461 MIL-STD-464 MIL-STD-704 DO-160 Requirements Management Jama DOORS Polarion Confluence Excel V&V Systems Engineering V-model AS9100 Hardware Qualification EMI/EMC +12 more Show less

SystemVerilog UVM VMM SerDes PCI Express USB SATA Python Perl C/C++ Assertion-based Verification Functional Coverage coverage driven verification Mixed-signal Design Simulation Debug +11 more Show less