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ASIC SoC RTL GDS2 FPGA SerDes DSP SPI I2C APB AXI Ethernet DFT Synthesis Timing Closure Low-Power Design Scripting +12 more Show less

ASIC Design RTL Design SystemVerilog Verilog Computer Architecture Synopsys Synthesis Low Power Design Python C++ C Coverage-based Design Verification SoC Interconnects Memory Controllers micro architecture Debugging +10 more Show less

ASIC SoC RTL GDS2 FPGA SerDes Ethernet SPI I2C APB AXI DFT Synthesis Timing Closure DSP Scripting +11 more Show less

ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Design Verification Scripting Logic Design +4 more Show less

ASIC Design RTL Coding Hardware Architecture LPDDR HBM NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Physical Design Gate Level Simulation Power Analysis Digital Design ISA Architecture +12 more Show less

ASIC Design RTL Coding Front-end Digital Design Hardware Architecture LPDDR HBM SRAM Cache Controller NoC x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis ISA Architecture +11 more Show less

Verilog SystemVerilog ASIC Design RTL Design Synopsys Synthesis Low Power Design Python C C++ Computer Architecture Coverage-based Design Verification SOC Interconnects Memory Controllers micro architecture +9 more Show less

Digital Design FPGA Emulation Silicon Bring-up Characterization Debug Mixed Signal Design MIPI HDMI Micro-architecture Verification Emulation TCON Display Pipeline +8 more Show less

Digital Design FPGA Emulation Silicon Bring-up Mixed Signal Design MIPI HDMI Micro-architecture Verification Emulation Validation TCON +6 more Show less

Digital Design ASIC FPGA Emulation Silicon Bring-up Mixed Signal Design MIPI HDMI TCON Micro-architecture Verification Emulation Validation Characterization Debug +9 more Show less