Senior Debug Engineer, PCIe/CXL, RAS, Memory

Amd

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Austin, TXBellevue, WASanta Clara, CA
Salary: $200,000–$300,000 / yr
Posted: 21 days ago
Freshness: Confirmed live today
Closes: Oct 5, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $195k

This role $250k

$134k $318k

below market most similar roles pay here above market

This role pays more than 92% of similar roles. Most pay $171,500–$217,525 — the blue band above. At the midpoint, this role pays about $250k versus about $195k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 496 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 496 roles with salary data.

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At a glance

TL;DR · Senior Debug Engineer, PCIe/CXL, RAS, Memory

Role Posting Log in to save

The Sr. Debug Engineer - PCIe/CXL, RAS, Memory joins the Server Customer Engineering team to drive customer issues to closure and deliver high-quality technologies. This role involves leading task forces to identify best solutions for failures related to RAS, PCIe, Memory, MCA, CXL, and Micro-Controller systems. The engineer will provide validation and debug recommendations, utilizing tools such as debug scripts, protocol analyzers, SCAN, and JTAG tools to narrow down and root cause failures during the bring-up, validation, and production phases of SOC programs. Key technical requirements include expertise in X86 micro architecture, post-silicon validation methodologies, and programming languages like Python, C++, Perl, and Ruby. The work focuses on resolving complex hardware and software issues within high-speed test and measurement environments for server systems.

Skills

RAS PCIe CXL Python C++ Perl Ruby JTAG SCAN Protocol Analyzers X86 micro architecture Post Silicon Validation MCA

What you'll do

Resolve customer failures related to RAS, PCIe, Memory, MCA, CXL, and Micro-Controller technologies.
Provide validation and debug recommendations to customers for new features and technical questions.
Use debug scripts, protocol analyzers, and SCAN/JTAG tools to identify and root cause customer failures.
Debug issues occurring during the bring-up, validation, and production phases of SOC programs.
Lead task forces and coordinate with multiple internal teams to identify and implement technical solutions.
Develop scripts using programming languages like Python to support debug and validation processes.

What we're looking for

Bachelor's or Master's degree in computer engineering or Electrical Engineering.
Experience in RAS, PCIe, Memory, MCA, CXL, and Micro-Controller related failures.
Experience utilizing debug tools such as debug scripts, protocol analyzers, SCAN, and JTAG tools.
Experience debugging issues during the process, bring-up, validation, and production phases of SOC programs.
10+ years of total experience inclusive of RAS, PCIe/CXL, MCA/MCE, or Memory validation and debug (preferred).
Experience of post silicon validation methodologies (preferred).
Experience developing programming languages such as Python scripts (preferred).
Experience handling high-speed test and measurement equipment such as protocol analyzers and scopes (preferred).