below marketmost similar roles pay hereabove market
This role pays less than
81%
of similar roles. Most pay
$162,000–$216,250
— the blue band above.
At the midpoint, this role pays about
$152k
versus about
$189k
for comparable roles.
Based on 240 similar postings.
Employer
About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has
575 open roles
on FindRole.
Listed pay typically runs
$147,900–$221,900
across 550 roles with salary data.
The Senior SoC Debug Engineer joins the Silicon Validation team within the central SoC digital hardware organization. This role focuses on ensuring the overall quality of the SoC silicon by supporting bring-up, debugging, and analyzing failures at the embedded platform level during both pre-Si and post-Si phases. The engineer will develop solutions for faster platform-level debug, isolate failing system components, and create debug strategies for partners to triage PVT and marginality issues. Key responsibilities include debugging low-level software and hardware issues while implementing Gen AI automation for debug flows. Required technical skills include RTL inspection, JTAG tools, and laboratory equipment such as logic analyzers, scopes, and signal generators. The role addresses critical hardware validation problems to ensure reliable silicon performance.
Perform bring-up and debug failures at the embedded platform level during pre-Si and post-Si phases.
Develop and implement solutions to accelerate platform-level debugging and isolate failing system components.
Create debug strategies and plans for partners to triage PVT and marginality issues.
Utilize Gen AI to automate and enable the debug flow.
Debug low-level software and hardware issues using JTAG and other debug tools.
Operate lab equipment including logic analyzers, scopes, and signal generators.
Perform RTL inspection and analysis to support hardware debugging.
What we're looking for
Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field.
5 to 8 years of experience with pre-si and post-silicon enabling, bring-up, and analyzing failures at the embedded platform level.
Proficiency in RTL inspection and understanding of basic RTL.
Experience with Gen AI for automating the debug flow.
Ability to debug low-level software and hardware issues using tools like JTAG and lab equipment like Logic Analyzers and Scopes.
Bachelor's degree in Computer Engineering and/or Electrical Engineering (preferred).