SoC Debug Engineer, Staff

Qualcomm

Confirmed live today High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$145,600–$218,400 / yr
Posted
11 days ago
Freshness
Confirmed live today
Closes
Apr 14, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $205k
This role $182k
$132k $274k
below market most similar roles pay here above market

This role pays less than 71% of similar roles. Most pay $177,250–$232,262 — the blue band above. At the midpoint, this role pays about $182k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · SoC Debug Engineer, Staff

JOB TITLE: SoC Debug Engineer, Staff The SoC Debug Engineer, Staff joins the Silicon Validation team within the ASICS Engineering group to support server, compute, and mobile chipsets. This role involves leading bring-up, debugging, and failure analysis at the embedded platform level during both pre-Si and post-Si phases. Key responsibilities include performing RTL inspection, root-causing JTAG and silicon exposure issues, and developing debug strategies for partners to triage PVT and marginality issues. The engineer will perform real-time troubleshooting of server hardware, including processors, memory, and networking components. Required skills include experience with JTAG, logic analyzers, scopes, and signal generators, along with proficiency in C, Assembly, Perl, and Python. The role focuses on solving complex hardware and low-level software issues, including server boot configurations and multi-die secure boot flows.

What you'll do

  • Lead bring-up and debug failures at the embedded platform level during pre-Si and post-Si phases.
  • Perform RTL inspection to root cause pre-Si debug issues and JTAG/Si exposure for post-Si issues.
  • Develop and lead initiatives to isolate failing system components and accelerate platform-level debugging.
  • Create debug strategies and plans for partners to triage failures, including PVT and marginality issues.
  • Perform real-time troubleshooting of server hardware including motherboards, processors, memory, and networking components.
  • Investigate manufacturing defects to determine root causes and implement corrective actions for product reliability.
  • Use lab equipment such as logic analyzers, scopes, and signal generators to debug low-level hardware and software.

What we're looking for

  • Master's degree in Computer Engineering and/or Electrical Engineering.
  • Bachelor's degree in Science, Engineering, or related field with 4+ years of ASIC design, verification, validation, or integration experience.
  • Master's degree in Science, Engineering, or related field with 3+ years of ASIC design, verification, validation, or integration experience.
  • PhD in Science, Engineering, or related field with 2+ years of ASIC design, verification, validation, or integration experience.
  • 6+ years of experience with pre-si and post-silicon enabling, bring-up, and analyzing failures at the embedded platform level.
  • Experience performing RTL inspection and debugging low-level software and hardware issues using JTAG and lab equipment.
  • Experience creating debug strategies and plans to triage failures, including PVT and marginality issues.
  • Strong programming in C, Assembly, Perl, or Python (preferred).

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