ASIC Engineering Technical Leader - DFT

Cisco

Actively hiring
Remote (Usa-San Jose, US) Posted 56 days ago $183,800–$263,600 / year
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At a glance

AI generated

TL;DR

As an ASIC Implementation Technical Lead at Cisco in San Jose, you will join the Silicon One development team to drive Design-for-Test (DFT) requirements early in the design cycle for next-generation networking chips. Your day-to-day responsibilities include implementing DFT features that support automated test equipment and in-system testing, collaborating with multi-functional teams to develop innovative DFT IP, and ensuring seamless integration of test logic throughout implementation and post-silicon validation phases. You will leverage JTAG protocols, Scan, BIST architectures, ATPG, and EDA tools like TestMax, Tetramax, Tessent, and PrimeTime, while also working with gate-level simulation and debugging using VCS simulators. The role demands a strong background in DFT, testability features, and silicon engineering, along with experience in post-silicon validation and ATE patterns.

Skills

Jtag Scan BIST ATPG TestMax Tetramax Tessent PrimeTime VCS Gate level simulation P1687 Verilog System Verilog Logic Equivalency checking DFT CAD development Test Static Timing Analysis

What you'll do

  • Implement Hardware Design-for-Test (DFT) features supporting Automatic Test Equipment (ATE).
  • Develop innovative DFT IP and integrate testability features in RTL with multi-functional teams.
  • Enable integration and validation of test logic throughout implementation and post-silicon phases.
  • Lead the creation of hardware DFT and physical design aspects for new silicon device models.
  • Craft solutions and debug issues with minimal guidance from mentors.

What we're looking for

  • At least 7 years of experience in DFT and silicon engineering.
  • Expertise in JTAG protocols, Scan, BIST architectures, and memory BIST.
  • Proficiency with EDA tools like TestMax, Tetramax, Tessent, and PrimeTime.
  • Experience in gate-level simulation and debugging using VCS and simulators.
  • Knowledge of post-silicon validation and ATE patterns.
  • Ability to develop innovative DFT IP and integrate test logic across design phases.

Market check

Salary context

This $183,800–$263,600 range sits above 80% of similar postings on FindRole.

Peer median band

$151,500–$221,800

Median floor and ceiling across peers.

Typical midpoint (25–75%)

$156,000–$216,250

Middle half of comparable postings.

Based on 240 comparable postings.

* 240 is the maximum number of comparable postings sampled.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 113 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 113 roles with salary data.

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