As a Senior Design for Test (DFT) Engineer in the Compute Silicon & Manufacturing Engineering organization at Microsoft, you will join a dynamic team focused on defining and delivering operational measures of success for hardware manufacturing. Your primary responsibilities include owning block-level DFT micro-architecture specifications, ensuring testability goals are met across IPs, maintaining and enhancing existing DFT tools with AI integration, and collaborating closely with verification engineers to perform waveform reviews. You will also work directly with test engineers to bring up test vectors and analyze yield and diagnosis issues. The role requires expertise in ATPG, JTAG, Memory BIST, and familiarity with EDA tools such as Siemens Tessent or Synopsys TestMax. Additionally, proficiency in Verilog/System Verilog, scripting languages like Tcl and Perl, and a proactive approach to problem-solving are essential for this high-impact position within the DFX (Test & Debug) team.
Own block level DFT micro-architecture specification documentation and provide test solutions.
Ensure DFX goals are met by reviewing coverage metrics for digital logic.
Maintain and enhance existing DFT tools to tailor solutions for current and upcoming products.
Provide test plans and engage with verification engineers for waveform reviews.
Enable silicon by working directly with test engineers to bring up test vectors and analyze yield.
What we're looking for
Doctorate in Electrical/Computer Engineering or related field with 1+ year of experience OR Master's with 4+ years OR Bachelor's with 5+ years.
4+ years of experience in Design for Test (DFT) including ATPG, JTAG, Memory BIST, and test quality/time trade-offs.
Expertise in Scan architecture, micro-arch specifications, and scan insertion techniques for IPs like PLLs, IOs, and Power circuits.
Proficiency with EDA tools such as Siemens Tessent or Synopsys TestMax for ATPG, stuck-at, at-speed insertion, boundary coverage, compression, and retargeting flows.
Knowledge of Verilog/System Verilog, simulators, waveform debugging tools, and scripting languages (Tcl & Perl).
Experience in Static Timing Analysis, constraint generation, ATE, silicon bring-up, and yield/diagnosis using Mentor Tessent/Synopsys tools.
Market check
Salary context
This
$119,800–$234,700
range sits above
74%
of similar postings on FindRole.
Peer median band
$119,800–$214,975
Median floor and ceiling across peers.
Typical midpoint (25–75%)
$142,400–$179,730
Middle half of comparable postings.
Based on 240 comparable postings.*
* 240 is the maximum number of comparable postings sampled.
Employer
About Microsoft
Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing
Microsoft currently has
451 open roles
on FindRole.
Listed pay typically runs
$119,800–$234,700
across 417 roles with salary data.
Altium Designer
Python
C
MS Office
Google Suite
MIL-STD
DMM
Bench top supply
Oscilloscope
Logic analyzer
Spectrum analyzer
USB 3.0
10Gb Ethernet
RS232
Xilinx FPGAs
HDI routing
Us, Ca, Santa Clara, US85 days ago
$136,000–$218,500
Perl
Python
Tcl
DFT
BIST
ATPG
fault simulation
vendor tools
RTL
STA
place-n-route
power management
Silicon debug
ATE
pattern formats
failure processing
test program development