ASIC Engineering Technical Leader- DFT

Cisco

Actively hiring
Remote (Usa-San Jose, US) Posted 77 days ago $210,600–$305,100 / year
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At a glance

AI generated

TL;DR

As an ASIC Implementation Technical Lead at Cisco in San Jose, you will join the Silicon One development team to drive Design-for-Test (DFT) requirements early in the design cycle for next-generation networking chips. Your day-to-day responsibilities include implementing DFT features that support Automatic Test Equipment (ATE), in-system testing, and debugging, while collaborating with front-end RTL teams and backend physical design teams to integrate test logic throughout all phases of implementation and post-silicon validation. You will leverage JTAG protocols, Scan, BIST architectures, ATPG, and EDA tools like TestMax, Tetramax, Tessent, and PrimeTime, requiring expertise in gate-level simulation with VCS and other simulators. This role demands a Bachelor's or Master's degree in Electrical or Computer Engineering with at least 10 years of experience in DFT, test, and silicon engineering, along with post-silicon validation and debug skills using ATE patterns.

Skills

Jtag Scan BIST ATPG TestMax Tetramax Tessent PrimeTime VCS Gate level simulation P1687 Verilog System Verilog Logic Equivalency checking DFT CAD development Test Static Timing Analysis Post-silicon validation

What you'll do

  • Implement Hardware Design-for-Test (DFT) features supporting ATE and in-system testing.
  • Develop innovative DFT IP and integrate testability features into RTL designs.
  • Collaborate with design/design-verification teams to validate Test logic throughout implementation phases.
  • Lead the creation of hardware DFT strategies for new silicon device models, including bare die and stacked die.
  • Drive re-usable test and debug strategies through the entire Implementation flow and post-silicon validation.

What we're looking for

  • At least 10 years of experience in DFT and silicon engineering.
  • Expertise in JTAG protocols, Scan, BIST architectures, including memory BIST.
  • Proficiency with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets.
  • Experience in gate level simulation and debugging using VCS and other simulators.
  • Knowledge of post-silicon validation and debug processes, ATE patterns.

Market check

Salary context

This $210,600–$305,100 range sits above 93% of similar postings on FindRole.

Peer median band

$151,500–$221,800

Median floor and ceiling across peers.

Typical midpoint (25–75%)

$156,000–$216,250

Middle half of comparable postings.

Based on 240 comparable postings.

* 240 is the maximum number of comparable postings sampled.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 113 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 113 roles with salary data.

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