ASIC Technical Lead- DFT

Cisco

Actively hiring
Remote (Usa-San Jose, US) Posted 43 days ago $210,600–$305,100 / year
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At a glance

AI generated

TL;DR

As an ASIC Implementation Technical Lead at Cisco in San Jose, CA, you will join the Silicon One development team to lead Design-for-Test (DFT) initiatives for next-generation networking chips. Your daily responsibilities include collaborating with front-end RTL and backend physical design teams to drive DFT requirements early in the design cycle, developing innovative DFT IP, and ensuring seamless integration of test logic throughout implementation and post-silicon validation phases. You will leverage JTAG protocols, Scan, BIST architectures, ATPG, and EDA tools like TestMax, Tetramax, and Tessent to craft solutions that enhance chip quality and reliability. This role demands expertise in Verilog design, functional verification, and test static timing analysis, with a focus on creating reusable test strategies for complex silicon devices.

Skills

Jtag Scan BIST ATPG TestMax Tetramax Tessent PrimeTime SystemVerilog Verilog Python Perl Makefile Git CI/CD PostgreSQL Docker Kubernetes

What you'll do

  • Implement Hardware Design-for-Test (DFT) features supporting Automatic Test Equipment and in-system testing.
  • Develop innovative DFT IP and integrate testability features into RTL designs with multi-functional teams.
  • Collaborate with design/design-verification and physical design teams for integration and validation of test logic.
  • Lead the creation of hardware DFT and physical design aspects for new silicon devices, including bare die and stacked die.
  • Craft solutions and debug issues in DFT and quality processes throughout implementation and post-silicon phases.

What we're looking for

  • At least 10 years of experience in ASIC implementation and DFT.
  • Expertise in JTAG protocols, scan, BIST architectures, and memory BIST.
  • Proficiency with EDA tools such as TestMax, Tetramax, Tessent, and PrimeTime.
  • Experience in ATPG, system Verilog logic equivalency checking, and test-timing validation.
  • Knowledge of DFT CAD development, including test architecture and infrastructure.
  • Familiarity with post-silicon validation using DFT patterns.

Market check

Salary context

This $210,600–$305,100 range sits above 94% of similar postings on FindRole.

Peer median band

$152,000–$225,850

Median floor and ceiling across peers.

Typical midpoint (25–75%)

$157,125–$216,250

Middle half of comparable postings.

Based on 240 comparable postings.

* 240 is the maximum number of comparable postings sampled.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 113 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 113 roles with salary data.

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