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Active Keyword: CPU RTL Power Engineer Remove filter Clear all

11 of up to 20 (filtered)

Next Gen CPU Power Management RTL Design Engineer

Amd

Santa Clara, CA 39 days ago $166,400–$249,600
Actively hiring Confirmed live yesterday High trust Competitive pay
Verilog SystemVerilog C++ C RTL Design Microarchitecture Power Management Clock Domain Crossing CDC Analysis Firmware DVFS Silicon Validation Design-for-Debug Design-for-Test Digital Design
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CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Waltham, MA 40 days ago $165,800–$292,400
Actively hiring Confirmed live today Trusted Competitive pay
RTL Verilog VHDL Microarchitecture C C++ Python Perl DVFS DVFM Formal Methods Simulation Emulation Waveform Debugging Logic Design Clock Generation Asynchronous Clock Crossing
10+ yrs exp
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CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 40 days ago $184,700–$324,800
Actively hiring Confirmed live today Trusted Above market
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl DVFS DVFM Formal Methods Simulation Emulation Waveform Debugging Logic Design Power Management Clock Generation Asynchronous Clock Crossing
10+ yrs exp
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CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Beaverton, OR 40 days ago
Actively hiring Confirmed live yesterday Low trust
RTL Verilog VHDL Microarchitecture C C++ Python Perl DVFS DVFM Formal Methods Simulation Emulation Waveform Debugging Logic Design Clock Generation Asynchronous Clock Crossing Power Integrity
10+ yrs exp
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CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 40 days ago $150,400–$277,600
Actively hiring Confirmed live today Trusted Competitive pay
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl DVFS DVFM Formal Methods Simulation Emulation Waveform Debugging Logic Design Power Management
3+ yrs exp
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CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 40 days ago $150,400–$277,600
Actively hiring Confirmed live today Trusted Competitive pay
RTL Verilog VHDL Microarchitecture CPU Power Management DVFS DVFM C C++ Python Perl Formal Methods Simulation Emulation Waveform Debugging Logic Design
3+ yrs exp
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CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Waltham, MA 40 days ago $165,800–$292,400
Actively hiring Confirmed live today Trusted Competitive pay
RTL Verilog VHDL Microarchitecture C C++ Python Perl DVFS DVFM Formal Methods Simulation Emulation Logic Design Power Management
10+ yrs exp
Save

CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 40 days ago $184,700–$324,800
Actively hiring Confirmed live today Trusted Above market
RTL Verilog VHDL Microarchitecture DVFS DVFM C C++ Python Perl Formal Methods Simulation Emulation Waveform Debugging Logic Design
10+ yrs exp
Save

CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Beaverton, OR 40 days ago
Actively hiring Confirmed live today Low trust
RTL Verilog VHDL Microarchitecture C C++ Python Perl DVFS DVFM Formal Methods Simulation Emulation Waveform Debugging Logic Design Clock Generation Asynchronous Clock Crossing
10+ yrs exp
Save

CPU RTL Power Engineer

Qualcomm

Austin, TX +1 40 days ago $155,400–$233,200
Actively hiring Confirmed live today Trusted Competitive pay
RTL Power Modeling PowerArtist PTPX Verilog VHDL Python Perl Low Power Design Clock Gating Logic Design Power Estimation Hardware Engineering
4+ yrs exp
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CPU RTL Power, Clocking, Reset Design Engineer

Amd

Fort Collins, CO 42 days ago $144,800–$217,200
Actively hiring Confirmed live today High trust Below market
RTL Design Verilog HDL Microarchitecture clock-domain crossing Power Management Voltage Management Scripting Tapeout Closure Design-for-Test Physical Design Control Fabric
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