CPU RTL Power Engineer

Qualcomm

Confirmed live 2 days ago Trusted

Quick summary

Work type
On-site
Location
Austin, TX
Salary
$148,300–$222,500 / yr
Posted
12 days ago
Freshness
Confirmed live 2 days ago
Closes
Feb 26, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $188k
This role $185k
$139k most similar roles pay here $235k

This role pays less than 53% of similar roles. Most pay $159,925–$216,250 — the shaded band above. At the midpoint, this role pays about $185k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · CPU RTL Power Engineer

The CPU RTL Power Engineer joins the CPU Engineering team to focus on high-performance, low-power device designs. In this role, you will own and participate in critical tasks including estimating and analyzing RTL power for CPU modules, creating comprehensive power models, and identifying early targets to ensure correlation with physical design. You will work across architecture, verification, and physical design teams to optimize power at various stages while analyzing power, performance, and area tradeoffs. The role requires expertise in active and idle power optimization, RTL clock gating techniques, and battery life projections. Essential skills include proficiency in Verilog or VHDL, experience with PowerArtist and PTPX tools, and the ability to develop Python or Perl scripts to automate estimation flows and analyze complex hardware throttling mechanisms to meet specific performance limits.

What you'll do

  • Estimate and analyze RTL power for CPU modules using PowerArtist or equivalent tools.
  • Optimize power at various design stages to meet specific performance targets.
  • Create comprehensive CPU power models to identify early targets and ensure correlation with physical design.
  • Analyze power, performance, and area tradeoffs for high-performance energy-efficient designs.
  • Develop Python or Perl scripts to automate power estimation and analysis workflows.
  • Create algorithms to analyze complex hardware throttling mechanisms for peak performance within power limits.
  • Implement low-power techniques including active/idle optimization and RTL clock gating.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • 3 to 8 years of experience in CPU RTL power modeling and estimation.
  • Deep understanding of CPU/ASIC low power design, including active/idle optimization and RTL clock gating.
  • Working knowledge of Verilog and/or VHDL with experience in tools like PowerArtist or PTPX.
  • Knowledge of logic design principles along with power and timing implications.
  • Proficiency in scripting languages such as Perl or Python for automation.

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