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Active Keyword: CPU RTL Power Remove filter Clear all

11 of up to 20 (filtered)

Next Gen CPU Power Management RTL Design Engineer

Amd

Santa Clara, CA 15 days ago $166,400–$249,600
Actively hiring Confirmed live today High trust Competitive pay
Verilog SystemVerilog C C++ RTL Design Microarchitecture Power Management Clock Domain Crossing DVFS Firmware Silicon Validation Lint CDC Analysis Digital Design Low-power Design
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CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 17 days ago $184,700–$324,800
Actively hiring Confirmed live today High trust Above market
RTL Verilog VHDL Microarchitecture DVFS DVFM C C++ Python Perl Simulation Emulation Power Management Logic Design
10+ yrs exp
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CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Beaverton, OR 17 days ago
Actively hiring Confirmed live today High trust
RTL Verilog VHDL Microarchitecture DVFS DVFM C C++ Python Perl Simulation Emulation Formal Methods Power Management Logic Design Waveform Debugging
10+ yrs exp
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CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 17 days ago $150,400–$277,600
Actively hiring Confirmed live today High trust Competitive pay
RTL Verilog VHDL Microarchitecture DVFS DVFM C C++ Python Perl Simulation Emulation Formal Methods Power Management Logic Design
3+ yrs exp
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CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 17 days ago $150,400–$277,600
Actively hiring Confirmed live today High trust Competitive pay
RTL Verilog VHDL Microarchitecture DVFS DVFM C C++ Python Perl Simulation Emulation Waveform Debugging Power Management Logic Design
3+ yrs exp
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CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Waltham, MA 17 days ago $165,800–$292,400
Actively hiring Confirmed live today High trust Competitive pay
RTL Verilog VHDL Microarchitecture DVFS DVFM C C++ Python Perl Simulation Emulation Formal Methods Waveform Debugging Logic Design Power Management
10+ yrs exp
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CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 17 days ago $184,700–$324,800
Actively hiring Confirmed live today High trust Above market
RTL Verilog VHDL Microarchitecture DVFS DVFM C C++ Python Perl Simulation Emulation Power Management Logic Design
10+ yrs exp
Save

CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Beaverton, OR 17 days ago
Actively hiring Confirmed live today High trust
RTL Verilog VHDL Microarchitecture DVFS DVFM C C++ Python Perl Simulation Emulation Formal Methods Power Management Logic Design
10+ yrs exp
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CPU RTL Power Engineer

Qualcomm

Austin, TX 17 days ago $155,400–$233,200
Actively hiring Confirmed live today Trusted Competitive pay
RTL Power Modeling PowerArtist PTPX Verilog VHDL Python Perl Clock Gating Logic Design Power Estimation
4+ yrs exp
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CPU RTL Power, Clocking, Reset Design Engineer

Amd

Fort Collins, CO 18 days ago $144,800–$217,200
Actively hiring Confirmed live today High trust Below market
RTL Design Verilog HDL Microarchitecture SoC Power Management Clocking Reset Clock-Domain Crossing Voltage-Domain Management Scripting Tapeout Physical Design
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