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Silicon Bring-up Post-silicon Python Perl Linux Android JMP AI LLM Prompt Engineering Oscilloscopes Multimeters PPA Analysis Data Analysis Scripting Automation +11 more Show less

Verilog system Verilog UVM Python C++ C Perl Shell MySQL PHP Linux Unix Windows HDL Digital Systems Computer Organization Hardware Design Simulation Debugging Oscilloscopes +15 more Show less

Verilog system Verilog UVM Python C++ C Perl Shell MySQL PHP Linux Unix Windows HDL Logic Design Simulation Debugging Oscilloscopes Logic Analyzers +14 more Show less

SystemVerilog UVM assertion based verification C++ Python Formal Verification UPF DDR Cache SoC tape out post silicon debug PASIM Power Verification +9 more Show less

SystemVerilog UVM Verilog SystemVerilog Assertions ASIC SoC Formal Verification UPF AXI APB AHB DFI JEDEC DDR LPDDR HBM Constrained-Random Verification Coverage-Driven Verification Simulation Waveform Analysis +15 more Show less

ASIC UVM SystemVerilog Verilog Python Perl VCS Verdi Xcelium Automation RTL Pre-silicon Verification Scripting Infrastructure Simulation Debug Metrics +12 more Show less

ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Verification Scripting Circuit Design Layout +5 more Show less

System Verilog UVM Verilog RTL C C++ Python Perl TCL DDR Memory Controller PHY Simulation Tools Code Coverage +9 more Show less

System Verilog UVM SVA Verilog VCS Questa Perl Tcl Make files Gate Level Simulation Formal Equivalence LLMs Agentic AI Frameworks Mixed Signal Design Functional Coverage Co-simulation +11 more Show less

SystemVerilog UVM assertion based verification C++ Python Formal Verification UPF DDR Cache SoC post silicon debug Power Verification PASIM Simulation +8 more Show less

SystemVerilog UVM VCS Verdi DVE Python Tcl Make PCIe Ethernet DDR AXI DMA Shell Perl C/C++ Formal Verification UPF FPGA HAPS +15 more Show less

SystemVerilog UVM VCS Verdi DVE Python Tcl Perl Shell PCIe Ethernet DDR AXI DMA UPF Formal Verification C/C++ Make HAPS FPGA +15 more Show less

SystemVerilog UVM VMM SerDes PCI Express USB SATA Python Perl C/C++ Assertion-based Verification Functional Coverage coverage driven verification Mixed-signal Design Simulation Debug +11 more Show less

System Verilog UVM Verilog VHDL C C++ Python Vulkan FPGA Emulation Palladium Zebu QEMU Make Airflow GDB uboot UEFI +13 more Show less