System Verification Co-Design Engineer - Speed and Reliability

Nvidia

Confirmed live 2 days ago High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Salary: $136,000–$218,500 / yr
Posted: 17 days ago
Freshness: Confirmed live 2 days ago
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $183k

This role $177k

$126k most similar roles pay here $228k

This role pays more than 52% of similar roles. Most pay $157,800–$208,900 — the shaded band above. At the midpoint, this role pays about $177k versus about $183k for comparable roles.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · System Verification Co-Design Engineer - Speed and Reliability

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As a System Verification Co-Design Engineer, you will join the SCG team to co-design system-level speed features and develop verification collaterals and automation infrastructure for characterization and validation. You will collaborate cross-functionally with architects, hardware, firmware, and software teams to translate architectural requirements into verification techniques while performing closed-loop validation by correlating silicon behavior against timing simulations. Your daily work involves defining pre- and post-silicon bring-up flows, designing automation tools for system speed modeling, and leading the debug of complex silicon issues to ensure on-time shipment. You will utilize Python, Perl, JMP, and lab instrumentation like oscilloscopes and multimeters within Windows, Linux, and Android environments. Additionally, you will integrate AI and LLM-assisted workflows for log analysis and scripting acceleration to optimize performance, power, and reliability across gaming, datacenter, automotive, and embedded markets.

Skills

Silicon Bring-up Post-silicon Python Perl Linux Android JMP AI LLM Prompt Engineering Oscilloscopes Multimeters PPA Analysis Data Analysis Scripting Automation

What you'll do

Co-design system-level speed features and define product requirements across multiple market segments.
Translate hardware features and architectural requirements into comprehensive verification techniques for full coverage.
Perform closed-loop validation by correlating silicon behavior against timing simulations and design expectations.
Define, prototype, and refine pre- and post-silicon bring-up flows to ensure performance and schedule efficiency.
Develop automation tools and AI/LLM-assisted workflows to accelerate characterization and debug cycles.
Architect and influence testability features critical to performance, power, and reliability in partnership with design teams.
Lead the debug of complex silicon issues and show-stopper defects to ensure on-time product shipment.

What we're looking for

MS in EE, CE, Systems Engineering, or equivalent experience.
4+ years of experience in a related hardware engineering role.
Hands-on experience with silicon bring-up, frequency and power characterization, and PPA analysis.
Experience with system/platform level understanding and tester-to-system correlation.
Proficiency with lab instrumentation including oscilloscopes, multimeters, and DAQs.
Scripting proficiency in Python and/or Perl within Windows, Linux, and Android environments.
Familiarity with statistical methods and data analysis tools like JMP or equivalent.
Demonstrated use of AI or LLM-based tools for engineering workflows such as scripting acceleration and log triage.