System Verification Co-Design Engineer, Speed and Rel

Nvidia

Confirmed live today High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Salary: $136,000–$218,500 / yr
Employment: Full-time
Posted: 34 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $196k

This role $177k

$125k $241k

below market most similar roles pay here above market

This role pays less than 62% of similar roles. Most pay $168,500–$224,125 — the blue band above. At the midpoint, this role pays about $177k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

Most-posted roles

View all roles at Nvidia

At a glance

TL;DR · System Verification Co-Design Engineer, Speed and Rel

Role Posting Log in to save

As a System Verification Co-Design Engineer, you will join the SCG team to co-design system-level speed features across Gaming, Datacenter, Automotive, and Embedded markets. You will develop verification collaterals and automation infrastructure to characterize and validate features, while leading the debug of complex silicon issues to ensure on-time shipment. Your daily work involves translating hardware requirements into verification techniques, performing closed-loop validation by correlating silicon behavior against timing simulations, and defining pre- and post-silicon bring-up flows. You will utilize Python, Perl, JMP, and lab instrumentation like oscilloscopes and multimeters. Additionally, you will implement AI and LLM-assisted workflows for automated log analysis and scripting acceleration. This role solves critical problems regarding system-level speed reliability margins, bounding box constraints, and performance optimization.

Skills

Python Perl Linux Windows Android AI LLM JMP Oscilloscope Multimeter Post-silicon PPA Analysis DFx ATE Scripting Data Analysis

What you'll do

Co-design system-level speed features and identify solutions to optimize performance and reliability margins.
Translate hardware features and architectural requirements into verification techniques to achieve full test coverage.
Perform closed-loop validation by correlating silicon behavior against timing simulations and design expectations.
Define and refine pre- and post-silicon bring-up flows to ensure product quality and schedule efficiency.
Design and implement automation tools for system speed modeling using AI and LLM-assisted workflows.
Architect testability features critical to performance, power, and reliability in partnership with design and ATE teams.
Lead debug of complex silicon and system-level issues to enable on-time product shipment.

What we're looking for

MS in EE, CE, Systems Engineering, or equivalent experience.
4+ years of experience in a related hardware engineering role.
Hands-on experience with silicon bring-up, frequency and power characterization, PPA analysis, and lab instrumentation.
Scripting proficiency in Python and/or Perl within Windows, Linux, and Android environments.
Familiarity with statistical methods and data analysis tools like JMP.
Demonstrated use of AI or LLM-based tools in an engineering workflow.
Background in gaming, automotive, or datacenter segments (preferred).
Experience building AI-assisted characterization or debug automation workflows in production silicon (preferred).

Similar roles

Low-Power Feature Validation & Bring-Up Engineer

Nvidia

Santa Clara, CA 34 days ago $168,000–$264,500

Python AI ML LLM Telemetry Silicon Validation Firmware Computer Architecture Digital Design Power Analysis Linux Windows Automation Data Analytics Post-Silicon Pre-Silicon S0ix ASPM RTD3

10+ yrs exp Hybrid

Save

System Verification Engineer

Nvidia

Austin, TX 11 days ago $108,000–$184,000

RTL Verification Python PCB Design Simulation ASIC FPGA System Validation Automation Mixed Signal Pre-silicon Verification System Design Gerber

Save

Senior System Verification Engineer

Nvidia

Austin, TX 11 days ago $136,000–$212,750

RTL Verification Verilog Python Simulation HSPICE PrimeSim PCB Design ASIC FPGA System Validation Pre-silicon Verification System Design Flows

5+ yrs exp

Save

Senior System Verification Engineer

Nvidia

Remote (Austin, TX) 11 days ago $200,000–$322,000

RTL Verification Mixed-Signal Simulation Python Verilog SPICE PCB Design Analog Simulation SOC Mixed-Signal Simulation PrimeSim System Validation Pre-silicon Verification ASIC FPGA System Design Flows

10+ yrs exp Remote

Save

SoC Design Verification Engineer

Amd

San Jose, CA 90 days ago $141,760–$212,640

System Verilog Verilog UVM C++ C Python Perl SOC Architecture Computer Architecture AXI AHB PCIe DDR Functional Verification Performance Verification Code Coverage Functional Coverage

Save

Design Verification Engineer, Memory Subsystem

Qualcomm

Santa Clara, CA 40 days ago $159,600–$239,400

SystemVerilog UVM Verilog SystemVerilog Assertions ASIC SoC Formal Verification Constrained-Random Verification Coverage-Driven Verification LPDDR DDR HBM JEDEC UPF AXI APB AHB DFI RTL Simulation

4+ yrs exp

Save