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Active Keyword: Next Gen Remove filter Location: San Diego Remove filter Clear all

10 of up to 20 (filtered)

Next-Gen System Cache ASIC Digital Design Engineer

Qualcomm

San Diego, CA 20 days ago $121,800–$182,600
Actively hiring Confirmed live today High trust Below market
ASIC Design RTL Design SystemVerilog Verilog Computer Architecture Synopsys Synthesis Low Power Design Python C++ C Coverage-based Design Verification SoC Interconnects Memory Controllers micro architecture Debugging
2+ yrs exp
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Next Gen High-Speed Memory and Cache Controller Design Engineer

Qualcomm

San Diego, CA 20 days ago $101,400–$152,200
Actively hiring Confirmed live today Trusted Below market
ASIC Design RTL LPDDR HBM DDR NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis Physical Design Micro-architecture ISA
3+ yrs exp
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Modem HW Design Engineer

Qualcomm

San Diego, CA 27 days ago $162,500–$243,700
Actively hiring Confirmed live today High trust Competitive pay
RTL Verilog SystemVerilog C/C++ SystemC Python Perl Unix Linux Shell Scripting DSP 4G 5G 3GPP ML Generative AI Synthesis LINT Clock Domain Crossing Low Power Design
4+ yrs exp
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Next-Gen High-Speed HBM LPDDR Memory Subsystem ASIC Digital Design Engineer

Qualcomm

San Diego, CA 40 days ago $145,600–$218,400
Actively hiring Confirmed live today Trusted Competitive pay
ASIC Design RTL Coding Hardware Architecture LPDDR HBM NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Physical Design Gate Level Simulation Power Analysis Digital Design ISA Architecture
4+ yrs exp
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Next-Gen High-Speed HBM LPDDR Memory Controller ASIC Digital Design Engineer

Qualcomm

San Diego, CA 40 days ago $145,600–$218,400
Actively hiring Confirmed live today Trusted Competitive pay
ASIC Design RTL Coding Front-end Digital Design Hardware Architecture LPDDR HBM SRAM Cache Controller NoC x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis ISA Architecture
4+ yrs exp
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Modem HW Design Engineer

Qualcomm

San Diego, CA +2 40 days ago $218,800–$328,200
Actively hiring Confirmed live yesterday High trust Above market
RTL Verilog SystemVerilog C/C++ SystemC Python Perl Unix Linux Shell Scripting DSP 3GPP 4G 5G ML Generative AI Synthesis LINT Makefiles XML
6+ yrs exp
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Next-Gen High-Speed Memory Subsystem ASIC Digital Design Engineer

Qualcomm

San Diego, CA 40 days ago $145,600–$218,400
Actively hiring Confirmed live today Trusted Competitive pay
Verilog SystemVerilog ASIC Design RTL Design Synopsys Synthesis Low Power Design Python C C++ Computer Architecture Coverage-based Design Verification SOC Interconnects Memory Controllers micro architecture
4+ yrs exp
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Staff SoC Performance Architect

Arm Holdings

San Jose, CA +1 140 days ago $209,100–$282,900
Actively hiring Confirmed live today Low trust Above market
SystemC TLM C++ Python HPC PCIe CXL InfiniBand RoCE Silicon Validation Memory Subsystems Architectural Modeling Benchmarking Methodologies
6+ yrs exp Hybrid
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Staff SoC Performance Architect

Arm Holdings

Austin, TX +1 140 days ago $209,100–$282,900
Actively hiring Confirmed live today Low trust Above market
SystemC TLM C++ Python HPC PCIe CXL InfiniBand RoCE Silicon Validation Memory Subsystems Simulation Environments
6+ yrs exp Hybrid
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