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ASIC Design VLSI CMOS Physical Design Floorplanning Placement Clock Tree Synthesis Routing Timing Closure DRC LVS IR/EM Checks RTL to GDSII UNIX Linux TCL Python Perl Cadence Innovus Synopsys ICC2 PrimeTime +16 more Show less

Python C++ Tcl Ruby Perl Verilog HDL UNIX Linux Digital Logic Design Static Timing Analysis Data Structures OO Design Synthesis Verification +9 more Show less

ASIC VLSI Floorplanning Physical Design TCL Python Perl Ruby Linux Cadence PPA Timing Closure IR/EM Analysis Power Grid Design Clock Distribution ECO Physical Verification +12 more Show less

Package Design ASIC SerDes HBM DDR5 Signal Integrity Power Integrity DFx Thermal Modeling Automation Project Management Layout Simulations RF Microwave ADC DAC +12 more Show less

IC Package Design Flip-chip BGA ASIC SerDes Signal Integrity Power Integrity HBM DDR5 Cadence APD Allegro Package Designer Cadence SKILL Physical Design Layout RF Microwave ADC DAC +12 more Show less

Python C++ Ruby Tcl Perl Verilog HDL Linux UNIX Digital Logic Design Static Timing Analysis Power Delivery Verification Data Structures OO Design ASIC Design Scripting +10 more Show less

Flip-chip-BGA ASIC SerDes HBM DDR5 Signal Integrity Power Integrity Layout DFx Thermal Modeling Automation Project Management Simulation RF Microwave +10 more Show less