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Active Keyword: ASIC Design and Integration Engineer Remove filter Location: Cupertino Remove filter Clear all

7 of up to 20 (filtered)

ASIC Design and Integration Engineer

Apple Inc

Cupertino, CA 7 days ago $150,400–$277,600
Actively hiring Confirmed live today Posted this week High trust Above market
Verilog RTL ASIC Design SOC Design Lint CDC RDC Synthesis ECO STA Physical Design Python Perl Tcl GenAI System Architecture
3+ yrs exp
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ASIC Design and Integration Engineer

Apple Inc

Cupertino, CA 7 days ago $184,700–$324,800
Actively hiring Confirmed live today Posted this week High trust Above market
Verilog RTL ASIC Design SOC Design CDC Lint Synthesis ECO Python Perl Tcl STA Physical Design GenAI System Architecture
10+ yrs exp
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ASIC Design and Integration Engineer

Apple Inc

Cupertino, CA 40 days ago $150,400–$277,600
Actively hiring Confirmed live today Trusted Above market
SystemVerilog RTL Design ASIC Design Synthesis Timing Analysis Formal Verification FPGA Prototyping PCIe CDC RDC LINT LEC Power Optimization Low-Power Design
3+ yrs exp
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ASIC Design and Integration Engineer, Silicon Security

Apple Inc

Cupertino, CA 68 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday High trust Above market
Verilog SystemVerilog RTL Design ASIC Design AMBA AXI AHB APB CDC RDC Lint Synthesis UPF Timing Closure Cryptography Low-Power Design Finite State Machines Pipelining
10+ yrs exp
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ASIC Design and Integration Engineer

Apple Inc

Cupertino, CA 78 days ago $129,300–$194,700
Actively hiring Confirmed live today Low trust Below market
SystemVerilog RTL Design ASIC Design Synthesis Formal Verification Simulation Timing Analysis Power Optimization CDC RDC Micro-architecture PPA
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ASIC Design and Integration Engineer, Silicon Security

Apple Inc

Cupertino, CA 84 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Trusted Above market
RTL Design Verilog SystemVerilog ASIC Design Synthesis Timing Closure UPF CDC RDC Lint AMBA AXI AHB APB Cryptography Hardware Security Low-Power Design Netlist
3+ yrs exp
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ASIC Design and Integration Engineer, Silicon Security

Apple Inc

Cupertino, CA 84 days ago $129,300–$194,700
Actively hiring Confirmed live today Trusted Below market
RTL Design Verilog SystemVerilog ASIC Design Micro-architecture Synthesis Timing Closure CDC RDC Lint UPF AMBA AXI AHB APB Cryptography Low-power Design Front-end Quality Flows
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