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Active Keyword: CPU Microarchitect Remove filter Location: Beaverton Remove filter Clear all

9 of up to 20 (filtered)

CPU Microarchitect/RTL Engineer, Execution, Load/Store

Apple Inc

Beaverton, OR 40 days ago
Actively hiring Confirmed live today Low trust
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Logic Design Formal Methods Simulation Emulation Out-of-Order Execution Instruction Scheduling Cache Memory Subsystems Waveform Debugging
10+ yrs exp
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CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Beaverton, OR 40 days ago
Actively hiring Confirmed live today Low trust
RTL Verilog VHDL Microarchitecture C C++ Python Perl DVFS DVFM Formal Methods Simulation Emulation Waveform Debugging Logic Design Clock Generation Asynchronous Clock Crossing Power Integrity
10+ yrs exp
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CPU Cache Microarchitect/RTL Engineer

Apple Inc

Beaverton, OR 40 days ago
Actively hiring Confirmed live today Low trust
RTL Verilog VHDL Microarchitecture C C++ Python Perl Formal Methods Simulation Emulation DFT SRAM Coherence Protocols Interconnects Power Management
10+ yrs exp
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CPU Microarchitect/RTL Engineer, Fetch, Out of Order

Apple Inc

Beaverton, OR 40 days ago
Actively hiring Confirmed live today Low trust
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Out-of-Order Execution Branch Prediction Instruction Fetch Register Renaming Formal Methods Simulation Emulation Waveform Debugging Logic Design
10+ yrs exp
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CPU MicroArchitect / RTL Engineer, Site Lead

Apple Inc

Beaverton, OR 40 days ago
Actively hiring Confirmed live today Low trust
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Logic Design Simulators Waveform Debugging Instruction Fetch and Decode Branch Prediction Out-of-Order Execution Cache and Memory Subsystems Low Power Microarchitecture
10+ yrs exp
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CPU Cache Microarchitect/RTL Engineer

Apple Inc

Beaverton, OR 40 days ago
Actively hiring Confirmed live today Low trust
RTL Verilog VHDL Microarchitecture C C++ Python Perl Formal Methods Simulation Emulation DFT SRAM Coherence Protocols Interconnects Power Management
10+ yrs exp
Save

CPU Microarchitect/RTL Engineer, Execution, Load/Store

Apple Inc

Beaverton, OR 40 days ago
Actively hiring Confirmed live today Low trust
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Formal Methods Simulation Emulation Out-of-Order Execution Instruction Scheduling Load/Store Execution Logic Design Waveform Debugging
10+ yrs exp
Save

CPU Microarchitect/RTL Engineer, Fetch, Out of Order

Apple Inc

Beaverton, OR 40 days ago
Actively hiring Confirmed live today Low trust
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Formal Methods Simulation Emulation Logic Design Instruction Fetch Branch Prediction Out-of-Order Execution Register Renaming Waveform Debugging
10+ yrs exp
Save

CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Beaverton, OR 40 days ago
Actively hiring Confirmed live today Low trust
RTL Verilog VHDL Microarchitecture C C++ Python Perl DVFS DVFM Formal Methods Simulation Emulation Waveform Debugging Logic Design Clock Generation Asynchronous Clock Crossing
10+ yrs exp
Save