Verification Engineer

What you'll do

• Develop SystemVerilog UVM and formal verification environments and tests for block-level functional verification.
• Create and maintain verification plans for assigned functional blocks throughout all engineering project phases.
• Generate and run tests on logic simulation models to identify design behavior.
• Investigate and debug functional issues in RTL using simulation and debug tools.
• Define and implement functional and statistical coverage to drive coverage closure.
• Improve and maintain testbenches to support high-quality CPU IP delivery.
• Resolve verification issues by analyzing CPU memory-system behavior with design and architecture colleagues.

What we're looking for

• Practical experience in pre-silicon design verification, including developing and debugging verification environments for RTL designs.
• Knowledge of CPU memory-subsystem microarchitecture, including load/store functionality, L2 cache, and memory management units.
• Experience applying simulation and/or formal verification methods to verify hardware functional units.
• Software engineering capability in object-oriented programming, data structures, and algorithms using SystemVerilog and UVM.
• Experience verifying high-performance CPU memory systems, including cache coherence, virtual memory, or out-of-order execution (preferred).
• Knowledge of processor microarchitecture concepts such as register renaming, reservation stations, or processor pipelines (preferred).
• Experience building reusable UVM testbenches and using functional coverage-driven verification methods (preferred).
• Experience with software engineering practices such as design patterns, profiling, unit testing, or programming in multiple languages (preferred).