Staff Design Verification Engineer, Coherent Interconnect

Arm Holdings

Confirmed live today High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Austin, TX
Salary: $198,100–$268,000 / yr
Posted: 2 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $199k

This role $233k

$136k $282k

below market most similar roles pay here above market

This role pays more than 77% of similar roles. Most pay $169,625–$229,100 — the blue band above. At the midpoint, this role pays about $233k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Arm Holdings

Arm Holdings plc is a leading British semiconductor and software design firm, established in 1990 and recognized for developing energy-efficient processor architectures that power nearly all smartphones and a vast range of IoT and computing devices.

Arm Holdings currently has 112 open roles on FindRole.

Listed pay typically runs $207,800–$281,200 across 112 roles with salary data.

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At a glance

TL;DR · Staff Design Verification Engineer, Coherent Interconnect

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The Staff Design Verification Engineer will join the team responsible for the Neoverse Coherent Mesh Network, a scalable system interconnect used in networking, storage, and AI applications. In this role, you will build and maintain detailed verification plans and strategies while collaborating with architects and designers to debug new features. Your daily responsibilities include architecting and developing efficient SystemVerilog and UVM based test benches, designing new stimulus and coverage, and driving improvements in verification methodology. You must possess experience in CPU microarchitecture, specifically cache coherence, memory systems, and bus protocols like AMBA CHI or ACE. The role requires proficiency in SystemVerilog/UVM constrained-random testbenches. Preferred skills include knowledge of PCIe, Compute Express Link, Formal Verification techniques, and scripting languages such as Python or Perl.

What does a Design Verification Engineer earn?

Median $191200 from 83 postings across 9 companies.

See salary data

Skills

SystemVerilog UVM RTL Design Formal Verification Python Perl AMBA CHI PCIe Compute Express Link Cache Coherence Memory Systems Bus Protocols

What you'll do

Build and maintain detailed verification plans and strategies.
Architect and develop efficient SystemVerilog/UVM based test benches.
Design new stimulus and coverage to ensure product quality.
Debug functional regression failures and close coverage gaps.
Develop and drive improvements in the verification methodology.
Debug and develop new features alongside architects and designers.

What we're looking for

Bachelor's, Master's, or PhD in Electrical/Computer Engineering or Computer Science.
8+ years of hands-on experience in verification or RTL design.
Experience in specification, creation, and debug of SystemVerilog/UVM constrained-random testbenches.
CPU microarchitecture experience including knowledge of cache coherence, memory systems, and bus protocols like AMBA CHI or ACE.
Applied knowledge and experience in PCIe or Compute Express Link (preferred).
Experience in Formal Verification techniques or scripting languages such as Python or Perl (preferred).

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