System FPGA Engineer

Qualcomm

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Santa Clara, CAAustin, TXFolsom, CAHillsboro, ORSan Diego, CA
Salary
$159,600–$239,400 / yr
Posted
40 days ago
Freshness
Confirmed live today
Closes
Mar 16, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $175k
This role $200k
$123k $252k
below market most similar roles pay here above market

This role pays more than 71% of similar roles. Most pay $142,500–$208,200 — the blue band above. At the midpoint, this role pays about $200k versus about $175k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · System FPGA Engineer

Role Posting Log in to save

JOB TITLE: System FPGA Engineer The System FPGA Engineer joins the Systems Engineering group to implement FPGA architectures for control-plane and telemetry systems on next-generation server reference platforms. This role involves translating specifications into synthesizable HDL, performing RTL development, simulation, verification, and lab bring-up. You will execute test benches, perform synthesis, place-and-route, and timing closure using vendor toolchains. Key technologies include Verilog, SystemVerilog, Python, and cocotb, alongside version control via git and GitHub. You will debug designs using JTAG, logic analyzers, and oscilloscopes while managing interfaces like I2C, UART, AXI4, PCIe, and DDR5. The work focuses on solving hardware integration challenges for server management standards such as IPMI, MCTP, PLDM, and OpenBMC ecosystems, ensuring high-quality RTL for complex multi-clock designs and high-speed SerDes.

Skills

FPGA Verilog SystemVerilog Python RTL cocotb CI/CD Git GitHub PCIe DDR5 AXI4 I2C UART SerDes Vivado Vitis Quartus Prime JTAG SDC XDC RISC-V IPMI MCTP PLDM

What you'll do

  • Implement RTL designs based on defined system architectures by translating specifications into synthesizable HDL.
  • Develop and execute test benches and verification plans for FPGA designs using industry-standard tools.
  • Perform FPGA synthesis, place-and-route, and timing closure using vendor-specific toolchains.
  • Test and debug FPGA designs in the lab using JTAG, logic analyzers, and oscilloscopes.
  • Develop Python-based scripts and cocotb test benches to support design automation and regression testing.
  • Identify implementation-level issues and provide technical feedback to architects regarding design specifications.
  • Maintain source-controlled design repositories using git and GitHub following team branching workflows.
  • Produce technical documentation covering implementation details, test results, and known issues.

What we're looking for

  • Bachelor's degree in Engineering, Computer Science, or related field and 4+ years of systems engineering experience.
  • Master's degree in Engineering, Computer Science, or related field and 3+ years of systems engineering experience.
  • PhD in Engineering, Computer Science, or related field and 2+ years of systems engineering experience.
  • 5+ years of experience in FPGA implementation and verification.
  • Proficiency in HDL development using Verilog and/or SystemVerilog for simulation, synthesis, and debugging.
  • Proficiency in Python scripting for design automation, test infrastructure, and cocotb test benches.
  • Experience with common interfaces such as I2C, UART, AXI4, PCIe, DDR5, or similar protocols.
  • Experience with FPGA development tools, hardware bring-up, and version control using git and GitHub.

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