Synthesis-DFT Stitch CAD Engineer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$164,000–$246,000 / yr
Posted
63 days ago
Freshness
Confirmed live yesterday
Closes
Jan 6, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $193k
This role $205k
$139k most similar roles pay here $257k

This role pays more than 57% of similar roles. Most pay $168,500–$218,081 — the shaded band above. At the midpoint, this role pays about $205k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Synthesis-DFT Stitch CAD Engineer

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The Synthesis-DFT Stitch CAD Engineer joins the Global CAD team to develop implementation tools and methodologies for Snapdragon chips. This role focuses on improving SoC Synthesis and DFT Stitch methods across Mobile, Compute, AI, and IoT platforms while managing complex multi-voltage crossings on DFT paths. The engineer will build and maintain regression testcases, interface with EDA vendors to ensure production-ready toolsets, and collaborate with internal teams to resolve block convergence issues like cell legalization and congestion hotspots. Key responsibilities include innovating techniques for area reduction and power optimization. The role requires expertise in Synthesis, DFT, and Place and Route, utilizing Synopsys and Cadence solutions. Candidates should possess proficiency in Python and TCL scripting languages while addressing technical challenges related to advanced process nodes and high-performance design goals.

Skills

Synthesis DFT Place and Route CAD Python TCL Synopsys Cadence VLSI GenAI PPA Multi-voltage ASIC Design EDA Tools

What you'll do

  • Develop and improve SoC Synthesis and DFT Stitch methodologies for mobile, compute, and AI chips.
  • Enable new features in EDA tools and internal tools for synthesis and DFT stitch checks.
  • Develop methods to handle complex multi-voltage crossings on DFT paths.
  • Resolve technical issues such as cell legalization, congestion hotspots, and DFT stitch failures.
  • Interface with EDA vendors to drive tool roadmaps and resolve block convergence problems.
  • Maintain a regression of complex DFT Stitch and Synthesis test cases.
  • Research and develop innovative techniques for area reduction, power reduction, and faster turnaround times.
  • Provide CAD solutions and technical support to Snapdragon design teams via ticket queues.

What we're looking for

  • Bachelor's degree in Science, Engineering, or a related field.
  • Master's degree in Science, Engineering, or a related field.
  • PhD in Science, Engineering, or a related field.
  • 5-10 years of experience in VLSI CAD, preferably Synthesis, DFT, and P&R.
  • 5-10 years of experience with scripting tools and programming languages like Python and TCL.
  • 6+ years of ASIC design, verification, validation, or integration experience for candidates with a Bachelor's degree.
  • 5+ years of ASIC design, verification, validation, or integration experience for candidates with a Master's degree.
  • 4+ years of ASIC design, verification, validation, or integration experience for candidates with a PhD.

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