below marketmost similar roles pay hereabove market
This role pays more than
61%
of similar roles. Most pay
$177,250–$241,750
— the blue band above.
At the midpoint, this role pays about
$218k
versus about
$210k
for comparable roles.
Based on 240 similar postings.
Employer
About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has
575 open roles
on FindRole.
Listed pay typically runs
$147,900–$221,900
across 550 roles with salary data.
The Synthesis-DFT Stitch CAD Engineer joins the Global CAD team to develop implementation tools and methodologies for Snapdragon chips. This role focuses on gate-level synthesis and DFT stitch solutions to optimize PPA, specifically targeting area reduction, dynamic power reduction, and turn-around time. Key responsibilities include developing DFT stitch flows, improving SoC synthesis methodologies for Mobile, Compute, AI, and IoT chips, and handling complex multi-voltage crossings. The engineer will interface with EDA vendors, manage ticket queues for design teams, and maintain regressions of complex testcases. Required technical skills include experience with Synopsys and Cadence tools, as well as proficiency in Python and TCL scripting. The work involves solving block convergence problems, cell legalization issues, and congestion hotspots using advanced process nodes and genAI/ML techniques.
Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
5-10 years of experience in VLSI CAD, preferably Synthesis, DFT and P&R (preferred).
5-10 years of experience with scripting tools and programming languages: Python and TCL preferred (preferred).
Experience with Synthesis, DFT, Place and Route, and CAD development skills.
Experience with Synopsys and Cadence solutions and tools.
Experience with multi-voltage crossings on DFT paths.