Staff PCB Layout Engineer

Arm Holdings

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Chandler, AZ
Salary
$198,100–$268,000 / yr
Posted
18 days ago
Freshness
Confirmed live today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $198k
This role $233k
$138k $282k
below market most similar roles pay here above market

This role pays more than 82% of similar roles. Most pay $170,869–$225,475 — the blue band above. At the midpoint, this role pays about $233k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Arm Holdings

Arm Holdings plc is a leading British semiconductor and software design firm, established in 1990 and recognized for developing energy-efficient processor architectures that power nearly all smartphones and a vast range of IoT and computing devices.

Arm Holdings currently has 113 open roles on FindRole.

Listed pay typically runs $208,450–$282,050 across 112 roles with salary data.

Most-posted roles

View all roles at Arm Holdings

At a glance

TL;DR · Staff PCB Layout Engineer

The Senior PCB Layout Engineer joins the Hardware Platforms team to create layouts for physical hardware development platforms used to evaluate custom system-on-chip designs. You will collaborate with hardware design teams to develop complex designs, managing mechanical and thermal requirements, footprint creation, component placement, and power plane optimization. Key responsibilities include routing high-speed parallel and serial signals and delivering data packs like ODB++, Gerber, and BOMs. You must possess experience with multi-layer, HDI PCBs, high-speed interfaces like PCIe and DDR, and high-density SoC escape routing. Proficiency in Cadence OrCAD CIS and Allegro PCB is required, alongside knowledge of IPC standards, Signal Integrity, and Power Integrity. You will also work with fabricators to ensure designs meet DFM and DFT standards for sophisticated compute platforms.

What you'll do

  • Create layouts for physical hardware development platforms to evaluate custom SoCs and reference designs.
  • Perform component placement and footprint creation based on mechanical and thermal requirements.
  • Optimize power planes and route high-speed parallel and serial signals.
  • Deliver final data packs including ODB++, Gerbers, fabrication and assembly drawings, and BOMs.
  • Design complex multi-layer and HDI PCBs with high pin count devices and high-speed interfaces.
  • Advise on pinout, routing topologies, and layer trade-off analysis for high-density SoCs.
  • Coordinate with fabricators and CEMs to ensure designs meet DFM, DFT, and automated assembly standards.
  • Provide technical advice to engineers regarding design rules, PCB fabrication, and substrate technologies.

What we're looking for

  • Experience designing complex, impedance-controlled multi-layer (>20), conventional, and HDI PCBs with high pin count devices (>2000).
  • Experience with high-speed interfaces (PCIe and DDR), differential pairs, and high-current PDNs.
  • Experience collaborating with chip packaging teams on pinout, routing topologies, cost optimization, and layer trade-off analysis.
  • Detailed knowledge of escape routing for high-density SoCs and FPGAs, including IO count estimates for specific stack-ups.
  • Extensive knowledge of PCB fabrication processes, IPC standards, substrate materials, via structures, and design rules.
  • Proficiency in Cadence OrCAD CIS and Allegro PCB.
  • Ability to collaborate with fabricators and CEMs for DFM/DFT and automated assembly.
  • Certified Interconnect Designer (CID, CID+) (preferred).

More like this

Similar roles

Staff PCB Layout Engineer

Arm Holdings

Chandler, AZ 18 days ago $198,100–$268,000
PCB Layout Cadence OrCAD CIS Allegro PCB HDI Signal Integrity Power Integrity PCIe DDR IPC Standards DFM DFT ODB++ Gerber Schematic Entry SoC FPGA
Hybrid

PCB Design Layout Engineer

Nvidia

Santa Clara, CA 26 days ago $168,000–$258,750
PCB Layout Cadence Allegro Mentor Graphics Signal Integrity Power Integrity High-Speed Digital Design ODB++ EMI/RFI Control IPC Specification FCC UL Electronic PCB Documentation CAD Layout Component Placement Constraints Management
6+ yrs exp

PCB Design Layout Engineer

Nvidia

Santa Clara, CA 26 days ago $168,000–$258,750
PCB Layout Cadence Allegro Mentor Graphics Signal Integrity Power Integrity High-Speed Digital Design EMI/RFI Control ODB++ IPC Specification FCC UL Electronic PCB Documentation CAD Layout Component Placement Constraints Management
6+ yrs exp

Staff PCB Designer/Layout Engineer, Air Dominance and Strike

Anduril Industries

Costa Mesa, CA 32 days ago $168,000–$272,000
Altium PCB Layout Power Integrity High Speed Digital DDR PCIe SerDes Ethernet USB HDI Microvia Rigid-flex RF Mixed-Signal HyperLynx Ansys SIwave Cadence Sigrity IPC Standards MIL-STD DFM DFA ECAD Libraries
10+ yrs exp

Staff PCB Design Engineer

Anduril Industries

Costa Mesa, CA 68 days ago $191,000–$253,000
PCB Design Altium Designer Allegro IPC Standards High-Speed Digital Power Electronics Flex Circuits HDI Power Integrity PCIe USB Ethernet SERDES DDR Memory FPGA DFM DFA
7+ yrs exp

PCB Design Layout Engineer

Nvidia

Santa Clara, CA 26 days ago $200,000–$322,000
PCB Layout Cadence Allegro HDI Signal Integrity DFM DFA DFT Back-drilling EMI/RFI Control IPC Specifications Floor Planning Constraint Management
10+ yrs exp