Senior PCB Layout Engineer

Arm Holdings

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Chandler, AZ
Salary
$198,100–$268,000 / yr
Posted
2 days ago
Freshness
Confirmed live today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $191k
This role $233k
$129k $283k
below market most similar roles pay here above market

This role pays more than 85% of similar roles. Most pay $165,000–$216,250 — the blue band above. At the midpoint, this role pays about $233k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Arm Holdings

Arm Holdings plc is a leading British semiconductor and software design firm, established in 1990 and recognized for developing energy-efficient processor architectures that power nearly all smartphones and a vast range of IoT and computing devices.

Arm Holdings currently has 110 open roles on FindRole.

Listed pay typically runs $207,800–$281,200 across 108 roles with salary data.

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View all roles at Arm Holdings

At a glance

TL;DR · Senior PCB Layout Engineer

The Senior PCB Layout Engineer joins the Hardware Platforms team to create layouts for physical hardware development platforms used to evaluate custom system-on-chip designs and reference designs. You will collaborate with hardware design teams to develop complex designs, managing mechanical and thermal requirements, footprint creation, component placement, and optimizing power planes and high-speed parallel and serial signal routing. Key responsibilities include delivering data packs like ODB++, Gerber, and BOMs while ensuring manufacturability. You must possess experience with multi-layer, HDI PCBs, high-speed interfaces like PCIe and DDR, and high-density SoC escape routing. Required technical skills include proficiency in Cadence OrCAD CIS and Allegro PCB, knowledge of IPC standards, and an understanding of Signal and Power Integrity. You will also coordinate with fabricators for DFM and DFT.

What you'll do

  • Create layouts for physical hardware development platforms used to evaluate custom SoCs and reference designs.
  • Develop complex designs including footprint creation, component placement, and power plane optimization.
  • Route high-speed parallel and serial signals while ensuring signal and power integrity.
  • Deliver final data packs including ODB++, Gerbers, fabrication and assembly drawings, and BOMs.
  • Design complex multi-layer and HDI PCBs with high pin count devices and high-current PDNs.
  • Advise on pinout, routing topologies, and layer trade-off analysis for high-density SoCs.
  • Coordinate with fabricators and CEMs to ensure designs align with DFM/DFT and supplier capabilities.
  • Provide technical advice to engineers regarding design rules, PCB fabrication, and substrate technologies.

What we're looking for

  • Experience designing complex, impedance-controlled multi-layer (>20), conventional, and HDI PCBs with high pin count devices (>2000).
  • Experience with high-speed interfaces (PCIe and DDR), differential pairs, and high-current PDNs.
  • Experience collaborating with chip packaging teams on pinout, routing topologies, cost optimization, and layer trade-off analysis.
  • Detailed knowledge of escape routing for high-density SoCs and FPGAs, including IO count estimates for specific stack-ups.
  • Extensive knowledge of PCB fabrication processes, IPC standards, stackup topologies, substrate materials, and design rules.
  • Proficiency in Cadence OrCAD CIS and Allegro PCB.
  • Ability to collaborate with fabricators and CEMs for DFM/DFT and automated assembly.
  • Certified Interconnect Designer (CID, CID+) (preferred).

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