Staff Engineer, Timing

What you'll do

• Perform hands-on timing analysis to ensure integrity and signoff readiness for complex GPU IPs.
• Generate and debug timing constraints for multi-clock designs across various functional and test scenarios.
• Develop and implement timing analysis and convergence strategies in collaboration with RTL, physical design, and SoC teams.
• Improve model extraction, timing convergence, correlation, and power recovery across advanced process nodes.
• Identify tool bugs and inefficiencies to improve flow, methodology, and overall timing predictability.
• Apply multi-voltage methodologies, timing budgeting, and derating techniques to achieve signoff readiness.
• Provide technical feedback to floorplan, clocking, and physical design teams to resolve block-level and full-chip issues.

What we're looking for

• Bachelor’s degree in Computer Science or Engineering with 6+ years experience, Master’s with 4+ years, or Ph.D. with 2+ years.
• Solid understanding and hands-on experience with ASIC design flows and electrical engineering fundamentals.
• Working knowledge of POCV, derating methodologies, and timing analysis.
• Strong hands-on experience with industry-standard STA tools such as PrimeTime or Tempus.
• Solid hands-on experience with clock tree synthesis (CTS), multi-voltage, and multi-clock designs.
• Working knowledge of formal equivalency checks, low-power checks, timing constraints, and UPF.
• Strong scripting and programming skills in Tcl, Perl, Shell, and/or Python.
• Authorization to access information subject to U.S. export control laws.