Staff Engineer, Static Timing Analysis CAD Engineer

Samsung Electronics

Confirmed live yesterday High trust
Remote

Quick summary

Work type
Remote
Location
Austin, TX
Salary
$151,000–$226,600 / yr
Posted
15 days ago
Freshness
Confirmed live yesterday
Closes
Oct 30, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $199k
This role $189k
$140k most similar roles pay here $250k

This role pays less than 57% of similar roles. Most pay $176,215–$222,000 — the shaded band above. At the midpoint, this role pays about $189k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Samsung Electronics

Samsung Electronics is a South Korean multinational corporation and a global leader in technology, specializing in consumer electronics, semiconductors, and home appliances.

Samsung Electronics currently has 94 open roles on FindRole.

Listed pay typically runs $106,000–$174,500 across 58 roles with salary data.

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View all roles at Samsung Electronics

At a glance

TL;DR · Staff Engineer, Static Timing Analysis CAD Engineer

As a Staff Engineer, Static Timing Analysis CAD Engineer, you will join the Advanced Design Technology and Design Implementation team to ensure timing integrity and signoff readiness for next-generation GPU IPs used in premium smartphones and other market segments. You will collaborate with design execution teams and EDA partners to develop automation, methodologies, and scalable solutions for complex advanced node designs. Your daily work involves implementing tools for timing analysis, managing multi-corner analysis, and addressing low-power constraints. The role requires expertise in ASIC design flows, LLE, POCV, and clock tree synthesis. You will utilize industry-standard tools such as PrimeTime, StarRC, PrimeClosure, and Tempus while leveraging scripting skills in Tcl, Python, Perl, and Shell. Your work addresses the technical challenge of achieving high-quality timing closure across functional and test modes for advanced semiconductor technology.

What you'll do

  • Ensure timing integrity and signoff readiness for next-generation GPU IPs across various market segments.
  • Develop and implement automated methodologies to streamline timing analysis for complex advanced node designs.
  • Create software-driven solutions to simplify execution, reduce errors, and maximize efficiency for STA teams.
  • Test and debug unexpected issues arising during new technology node bring-up processes.
  • Improve timing quality and predictability by applying POCV, multi-corner analysis, and low-power constraints.
  • Develop scripts in Tcl, Python, Perl, or Shell to automate repetitive engineering tasks.
  • Document technical designs, methodologies, and best practices for internal and external stakeholders.
  • Utilize AI tools to improve efficiency in daily engineering tasks and project execution.

What we're looking for

  • Bachelor's degree with 6+ years experience, Master's with 4+ years, or Ph.D. with 2+ years of experience in a related field.
  • Solid understanding and hands-on experience with ASIC design flows and electrical engineering fundamentals.
  • Working knowledge and experience with LLE, POCV, derating methodologies, and timing analysis.
  • Strong hands-on experience with industry-standard STA tools such as PrimeTime, StarRC, PrimeClosure, and Tempus.
  • Solid hands-on experience with clock tree synthesis (CTS), multi-voltage designs, and multi-clock designs.
  • Working knowledge of formal equivalency checks, low-power checks, timing constraints, and UPF.
  • Strong scripting and programming skills in Tcl, Python, Perl, and Shell script.
  • Applicants must be authorized to access information subject to U.S. export control laws.

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