This role pays less than
70%
of similar roles. Most pay
$172,000–$222,000
— the shaded band above.
At the midpoint, this role pays about
$177k
versus about
$197k
for comparable roles.
Based on 240 similar postings.
Employer
About Amd
AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors
Amd currently has
367 open roles
on FindRole.
Listed pay typically runs
$166,400–$249,600
across 367 roles with salary data.
As a Sr. Timing Methodology Engineer within the Adaptive and Embedded Computing Group, you will define, develop, and drive timing and power methodologies for advanced process nodes. You will work closely with architecture, product planning, process, design, and product engineering teams to realize silicon solutions with best-in-class PPA. Your daily work involves solving pressing challenges in sign-off and modeling methodologies at 2nm and beyond on monolithic and 2.5/3DIC adaptive SOCs and FPGAs. You will collaborate with CAD, power integrity, foundry teams, and EDA vendors to understand margins and develop mitigation strategies. The role requires expertise in industry-standard physical design, analysis, and sign-off tools, as well as FPGA implementation tools. Technical skills include proficiency in Python, Perl, and Tcl to support the development of methodologies for the design community.