Staff Board Package Co-design Engineer

Arm Holdings

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Chandler, AZ
Salary: $198,100–$268,000 / yr
Posted: 34 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $215k

This role $233k

$156k most similar roles pay here $280k

This role pays more than 68% of similar roles. Most pay $182,000–$247,150 — the shaded band above. At the midpoint, this role pays about $233k versus about $215k for comparable roles.

Based on 240 similar postings.

Employer

About Arm Holdings

Arm Holdings plc is a leading British semiconductor and software design firm, established in 1990 and recognized for developing energy-efficient processor architectures that power nearly all smartphones and a vast range of IoT and computing devices.

Arm Holdings currently has 105 open roles on FindRole.

Listed pay typically runs $209,100–$282,900 across 105 roles with salary data.

Most-posted roles

View all roles at Arm Holdings

At a glance

TL;DR · Staff Board Package Co-design Engineer

Role Posting Log in to save

Staff Board - Package co-design Engineer joins the Packaging, Boards and Multiphysics team to develop physical hardware platforms for software development and validation of Arm IP products. This role focuses on the integration of PCB and silicon packaging for System-on-Chip designs. You will collaborate with global teams to influence silicon architecture, evaluate package pinout trade-offs, and manage breakout and routing strategies. Key responsibilities include analyzing signal paths for high-speed standards like PCIe and LPDDR memory, performing Signal and Power Integrity analysis, and assessing PCB manufacturability through PTH and HDI technologies. You will utilize Cadence OrCAD and Allegro tools to ensure optimal performance and cost-effectiveness. The role addresses the technical challenges of embedded compute by optimizing signal quality and power delivery while navigating complex constraints in high-density SoC designs and advanced substrate materials.

Skills

PCB Design Silicon Packaging SoC) integration High-Speed Design Cadence OrCAD Allegro PCIe LPDDR HDI EDA Tools ANSYS Siemens EDA Scripting Design Automation

What you'll do

Develop solutions for efficient PCB and silicon package integration to influence architecture and pinout trade-offs.
Drive PCB development including breakout strategies, design rules, and layer optimization for performance and cost-effectiveness.
Analyze and optimize high-speed signal paths to ensure quality and minimize noise for PCIe and LPDDR technologies.
Perform escape routing analysis for high-density SoCs to estimate routable IO counts based on specific stack-ups.
Conduct Signal and Power Integrity (SI/PI) analysis from both board design and chip packaging perspectives.
Assess the manufacturability of advanced PCB technologies in collaboration with fabricators and CEM partners.
Evaluate package pinout options against routability, SI/PI performance, layer count, and manufacturing constraints.
Support early silicon and board architecture planning including component placement, form-factor constraints, and PDN strategy.

What we're looking for

Strong understanding of electronics and embedded compute systems.
Familiarity with IC packaging technologies and their impact on PCB design for SoC integration.
Experience collaborating with chip packaging teams to influence SoC device pin-outs for cost and routing feasibility.
Detailed knowledge of high-speed design and interface standards, including PCIe and LPDDR memory technologies.
Expertise in escape routing analysis of high-density SoCs and providing IO count estimates based on stack-up and design rules.
Extensive knowledge of Signal and Power Integrity analysis techniques from both board design and chip packaging perspectives.
Understanding of PCB fabrication processes (PTH and HDI), stackup/VIA topologies, and substrate materials.
Proficiency in Cadence OrCAD and Allegro for schematic entry and PCB layout.
Experience using Signal Integrity tools from ANSYS or Siemens EDA (preferred).
Experience in design automation and scripting (preferred).

Similar roles

Principal Engineer - Board/Package Co-design

Arm Holdings

Chandler, AZ 17 days ago $249,900–$338,100

PCB Design SoC Architecture Signal Integrity Power Integrity Cadence OrCAD Allegro PCIe LPDDR5 FPGA PMIC HDI EDA Tools ANSYS Siemens EDA High-Speed IO Silicon Packaging

Save

Principal Engineer - Board/Package Co-design

Arm Holdings

Chandler, AZ 8 days ago $249,900–$338,100

PCB Design SoC Architecture Signal Integrity Power Integrity Cadence OrCAD Allegro PCIe LPDDR5 FPGA PMIC HDI EDA Tools ANSYS Siemens EDA High-Speed IO Silicon Packaging

Save

Principal Engineer - Board/Package Co-design

Arm Holdings

Chandler, AZ 51 days ago $249,900–$338,100

PCB Design SoC Architecture Signal Integrity Power Integrity Cadence OrCAD Allegro PCIe LPDDR5 FPGA HDI EDA Tools ANSYS Siemens EDA IC Packaging High-Speed IO PMIC

Save

Principal Engineer - Board/Package Co-design

Arm Holdings

Chandler, AZ 34 days ago $249,900–$338,100

PCB Design SoC Architecture Signal Integrity Power Integrity Cadence OrCAD Allegro PCIe LPDDR5 FPGA HDI IC Packaging EDA Tools ANSYS Siemens EDA PMICs

Save

Package Design Engineer, Staff

Qualcomm

San Diego, CA 15 days ago $160,200–$240,200

Cadence APD Siemens Xpedition Cadence Allegro SiP SI/PI DRC DFM ERC XtractIM PowerSI HFSS Q3D Calibre DDR PCIe UCIe S-parameters RLGC High-speed IO

5+ yrs exp

Save

Staff Package Layout Engineer

Arm Holdings

San Jose, CA 20 days ago $209,100–$282,900

Cadence APD Allegro SI/PI DFM DFA Python SKILL TCL Power Delivery Networks Package Routing Stack-up Creation

Hybrid

Save