Principal Engineer, PCB/Package Co-design

Arm Holdings

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Chandler, AZ
Salary
$249,900–$338,100 / yr
Posted
6 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $199k
This role $294k
$123k most similar roles pay here $361k

This role pays more than 97% of similar roles. Most pay $160,581–$237,800 — the shaded band above. At the midpoint, this role pays about $294k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Arm Holdings

Arm Holdings plc is a leading British semiconductor and software design firm, established in 1990 and recognized for developing energy-efficient processor architectures that power nearly all smartphones and a vast range of IoT and computing devices.

Arm Holdings currently has 50 open roles on FindRole.

Listed pay typically runs $209,100–$282,900 across 50 roles with salary data.

Most-posted roles

View all roles at Arm Holdings

At a glance

TL;DR · Principal Engineer, PCB/Package Co-design

As a Principal Engineer - PCB/Package Co-design, you will join the Packaging, Boards and Multiphysics team to develop physical hardware development platforms based around custom Arm SoC. You will collaborate with global engineering groups to define technical requirements, evaluate design trade-offs, and integrate silicon packaging with PCB designs. Your daily work involves brainstorming breakout strategies, routing, and layer optimization while ensuring signal and power integrity for high-performance embedded compute, Cloud/Edge AI, and IoT systems. You will utilize Cadence OrCAD and Allegro tools to manage schematic entry and layout. Key technical requirements include experience with high-speed IO standards like PCIe Gen5/6/7 and LPDDR5/6, as well as expertise in HDI fabrication processes and escape routing analysis for high-density SoCs. You will bridge the gap between silicon packaging and board design to optimize cost, performance, and manufacturability.

What does a Engineer earn?

Median $180500 from 267 postings across 57 companies.

See salary data

What you'll do

  • Develop solutions for efficient PCB and silicon package integration to ensure optimal performance and cost-effectiveness.
  • Drive PCB development including breakout, routing strategies, design rules, and layer optimization.
  • Translate technical requirements from SoC teams into viable platform architectures.
  • Influence and drive SoC device pin-outs based on routing feasibility and layer trade-off analysis.
  • Perform escape routing analysis for high-density SoCs to estimate routable IO counts.
  • Conduct Signal and Power Integrity (SI/PI) analysis from both board design and chip packaging perspectives.
  • Assess the manufacturability of advanced PCB technologies in collaboration with fabricators and partners.
  • Support early silicon and board architecture definition including component placement, form-factor constraints, and PDN strategy.

What we're looking for

  • Deep technical understanding of SoC architectures for high-performance embedded compute, Cloud/Edge AI, and IoT.
  • Experience with high-speed IO interface standards such as PCIe Gen5/6/7, LPDDR5/6, CSI, and DSI.
  • Competence in embedded system board design involving complex LSI devices like FPGAs, firmware, and PMICs.
  • Familiarity with IC packaging technologies and their impact on PCB design for signal routing and power delivery.
  • Experience collaborating with chip packaging teams to influence SoC device pin-outs and evaluate trade-offs.
  • Expertise in escape routing analysis of high-density SoCs and Signal/Power Integrity analysis techniques.
  • Knowledge of PCB fabrication processes, including PTH, HDI, stackup topologies, and substrate materials.
  • Proficiency in EDA tools for schematic entry and PCB layout such as Cadence OrCAD and Allegro.
  • Experience using Signal Integrity tools from ANSYS or Siemens EDA (preferred).
  • Fundamental understanding of compute architectures and functional building blocks (preferred).
  • Experience working within the semiconductor industry (preferred).

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