Principal Engineer

Arm Holdings

Confirmed live 2 days ago Trusted
Hybrid

Quick summary

Work type
Hybrid
Location
Chandler, AZ
Salary
$249,900–$338,100 / yr
Posted
7 days ago
Freshness
Confirmed live 2 days ago

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $201k
This role $294k
$119k $362k
below market most similar roles pay here above market

This role pays more than 91% of similar roles. Most pay $174,600–$228,062 — the blue band above. At the midpoint, this role pays about $294k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Arm Holdings

Arm Holdings plc is a leading British semiconductor and software design firm, established in 1990 and recognized for developing energy-efficient processor architectures that power nearly all smartphones and a vast range of IoT and computing devices.

Arm Holdings currently has 113 open roles on FindRole.

Listed pay typically runs $208,450–$282,050 across 112 roles with salary data.

Most-posted roles

View all roles at Arm Holdings

At a glance

TL;DR · Principal Engineer

JOB TITLE: Principal Engineer The Principal Engineer joins the Packaging, Boards and Multiphysics team to help craft next-generation hardware platforms. This role involves collaborating with SoC teams and architects to define technical requirements and develop solutions for efficient PCB and silicon package integration. You will drive PCB development, including breakout, routing strategies, and layer optimization to ensure performance and cost-effectiveness. Key responsibilities include performing escape routing analysis, Signal and Power Integrity analysis, and evaluating package pinouts against routability and manufacturability. You will utilize Cadence OrCAD and Allegro for schematic entry and PCB layout. The role requires expertise in high-speed IO standards like PCIe Gen5/6/7 and LPDDR5/6, as well as experience with FPGAs, PMICs, and advanced PCB fabrication processes like HDI and PTH.

What does a Engineer earn?

Median $178175 from 251 postings across 54 companies.

See salary data

What you'll do

  • Specify and develop solutions for efficient PCB and silicon package integration.
  • Drive PCB development including breakout, routing strategies, design rules, and layer optimization.
  • Translate technology requirements into platform architectures for SoC development teams.
  • Perform escape routing analysis for high-density SoCs to estimate routable IO counts.
  • Conduct Signal and Power Integrity analysis from both board design and chip packaging perspectives.
  • Evaluate package pinout options against routability, SI/PI performance, and manufacturability.
  • Support early silicon and board architecture definition including component placement and PDN strategy.
  • Use EDA tools for schematic entry and PCB layout in Cadence OrCAD and Allegro.

What we're looking for

  • Deep technical background in SoC architectures for high-performance embedded compute, Cloud/Edge AI, and IoT.
  • Experience with high-speed IO standards including PCIe Gen5/6/7, LPDDR5/6, CSI, and DSI.
  • Competence in embedded system board design with FPGAs, embedded firmware, and power management ICs.
  • Familiarity with IC packaging technologies and their impact on PCB design, signal routing, and power delivery.
  • Expertise in escape routing analysis for high-density SoCs and providing IO count estimates for specific stack-ups.
  • Extensive knowledge of Signal and Power Integrity analysis techniques for both board design and chip packaging.
  • Proficiency in using EDA tools for schematic entry and PCB layout, specifically Cadence OrCAD and Allegro.
  • Experience using Signal Integrity tools from ANSYS or Siemens EDA (preferred).

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