Principal Board Package Co-design Architect

What you'll do

• Develop solutions for efficient PCB and silicon package integration to ensure optimal performance and cost-effectiveness.
• Drive PCB development including breakout, routing strategies, design rules, and layer optimization.
• Translate technical requirements from SoC teams into viable platform architectures.
• Influence and drive SoC device pin-outs based on routability, cost optimization, and layer trade-off analysis.
• Perform escape routing analysis for high-density SoCs to estimate IO counts for specific stack-ups.
• Conduct Signal and Power Integrity (SI/PI) analysis from both board design and chip packaging perspectives.
• Assess the manufacturability of advanced PCB technologies in collaboration with fabricators and partners.
• Support early silicon and board architecture definition including component placement, form-factor constraints, and PDN strategy.

What we're looking for

• Deep technical understanding of SoC architectures for high-performance embedded compute, Cloud/Edge AI, and IoT.
• Experience with high-speed IO interface standards such as PCIe Gen5/6/7, LPDDR5/6, CSI, and DSI.
• Competence in embedded system board design involving FPGAs, embedded firmware, and power management ICs (PMICs).
• Familiarity with IC packaging technologies and their impact on PCB design for signal routing and power delivery.
• Experience collaborating with chip packaging teams to influence SoC device pin-outs and trade-off analysis.
• Expertise in escape routing analysis of high-density SoCs and Signal/Power Integrity analysis techniques.
• Knowledge of PCB fabrication processes (PTH, HDI), stackup topologies, and substrate materials.
• Proficiency in EDA tools for schematic entry and PCB layout, specifically Cadence OrCAD and Allegro.