Staff Package Layout Engineer

Arm Holdings

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CA
Salary
$209,100–$282,900 / yr
Posted
20 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $209k
This role $246k
$146k most similar roles pay here $298k

This role pays more than 82% of similar roles. Most pay $179,325–$238,250 — the shaded band above. At the midpoint, this role pays about $246k versus about $209k for comparable roles.

Based on 240 similar postings.

Employer

About Arm Holdings

Arm Holdings plc is a leading British semiconductor and software design firm, established in 1990 and recognized for developing energy-efficient processor architectures that power nearly all smartphones and a vast range of IoT and computing devices.

Arm Holdings currently has 105 open roles on FindRole.

Listed pay typically runs $209,100–$282,900 across 105 roles with salary data.

Most-posted roles

View all roles at Arm Holdings

At a glance

TL;DR · Staff Package Layout Engineer

As a Staff Package Layout Engineer within the System-in-Package team, you will contribute to implementing next-generation SoCs for the IoT, Automotive, and Compute spaces. You will be responsible for the definition, design, and verification of package designs while managing complex 2.5D and 3D technologies. Your daily work involves creating layouts using best practices for DFM, DFA, and Signal and Power Delivery Networks, conducting feasibility studies for size and cost, and optimizing bump-maps and ball patterns. You will utilize the Cadence APD and Allegro toolsets to implement routing, stack-up creation, and power distribution. The role requires expertise in SI/PI requirements and potentially includes programming in Python, SKILL, or TCL. You will collaborate with global teams and vendors to solve technical problems and improve layout team efficiency through new methodologies.

What you'll do

  • Design and verify next-generation SoC package designs using 2.5D and 3D technologies.
  • Create layouts following best practices for DFM, DFA, Signal, and Power Delivery Networks.
  • Conduct design feasibility studies to evaluate goals for size, cost, and system performance.
  • Optimize package bump-maps and ball patterns based on technical feasibility studies.
  • Implement package routing, stack-up creation, and power distribution using Cadence APD or SiP tools.
  • Develop and test new methodologies to improve the efficiency of the layout team.
  • Coordinate with external vendors and internal teams to resolve design challenges.

What we're looking for

  • An Electrical Engineering degree or equivalent work experience.
  • Experience with 2.5D and 3D package systems and their SI/PI requirements.
  • 5-7+ years of recent experience in the use of Cadence APD & Allegro toolsets.
  • Ability to conduct design feasibility studies for size, cost, and system performance.
  • Familiarity with EDA vendor collaboration, tool evaluations, and issue resolution (preferred).
  • Strong verbal, written communication, and presentation skills (preferred).
  • Programming experience in Python, SKILL, or TCL (preferred).

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