Principal Engineer - Board/Package Co-design

Arm Holdings

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Chandler, AZ
Salary
$249,900–$338,100 / yr
Posted
8 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $212k
This role $294k
$138k most similar roles pay here $360k

This role pays more than 91% of similar roles. Most pay $181,010–$242,847 — the shaded band above. At the midpoint, this role pays about $294k versus about $212k for comparable roles.

Based on 240 similar postings.

Employer

About Arm Holdings

Arm Holdings plc is a leading British semiconductor and software design firm, established in 1990 and recognized for developing energy-efficient processor architectures that power nearly all smartphones and a vast range of IoT and computing devices.

Arm Holdings currently has 105 open roles on FindRole.

Listed pay typically runs $209,100–$282,900 across 105 roles with salary data.

Most-posted roles

View all roles at Arm Holdings

At a glance

TL;DR · Principal Engineer - Board/Package Co-design

As a Principal Engineer - Board/Package Co-design, you will join the Packaging, Boards and Multiphysics team to develop physical hardware development platforms based around custom Arm SoC. You will collaborate with global engineering groups to define technical requirements, evaluate design trade-offs, and integrate PCB and silicon packaging solutions. Your daily work involves brainstorming breakout strategies, routing, and layer optimization while translating technology requirements into platform architectures. You will manage signal and power integrity analysis, assess manufacturability of advanced PCB technologies, and evaluate package pinout options against cost and routability. The role requires expertise in high-speed IO standards like PCIe and LPDDR, experience with complex LSI devices, and proficiency in Cadence OrCAD and Allegro tools. You will solve critical integration challenges for embedded compute systems across the Cloud, Edge AI, and IoT domains.

What does a Engineer earn?

Median $185000 from 207 postings across 51 companies.

See salary data

What you'll do

  • Develop solutions for efficient PCB and silicon package integration to ensure optimal performance and cost-effectiveness.
  • Drive PCB development including breakout, routing strategies, design rules, and layer optimization in coordination with packaging teams.
  • Translate complex technology requirements into functional platform architectures for SoC development teams.
  • Perform escape routing analysis for high-density SoCs to determine IO counts based on specific stack-ups and design rules.
  • Conduct Signal and Power Integrity (SI/PI) analysis from both board design and chip packaging perspectives.
  • Evaluate package pinout options against routability, SI/PI performance, manufacturability, and cost constraints.
  • Support early silicon and board architecture definition including component placement, form-factor constraints, and PDN strategy.
  • Use EDA tools for schematic entry and PCB layout to develop hardware development platforms.

What we're looking for

  • Deep technical understanding of SoC architectures for high-performance embedded compute, Cloud/Edge AI, and IoT.
  • Experience with high-speed IO interface standards such as PCIe Gen5/6/7, LPDDR5/6, CSI, and DSI.
  • Competence in embedded system board design involving complex LSI devices like FPGAs, firmware, and PMICs.
  • Familiarity with IC packaging technologies and their impact on PCB design for signal routing and power delivery.
  • Experience collaborating with chip packaging teams to influence SoC device pin-outs and evaluate trade-offs.
  • Expertise in escape routing analysis of high-density SoCs and Signal/Power Integrity analysis techniques.
  • Knowledge of PCB fabrication processes, stackup topologies, and ability to assess manufacturability with partners.
  • Proficiency in Cadence OrCAD and Allegro for schematic entry and PCB layout.
  • Experience using Signal Integrity tools from ANSYS or Siemens EDA (preferred).
  • Fundamental understanding of compute architectures and functional building blocks (preferred).
  • Experience working within the semiconductor industry (preferred).

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