STA Engineer

Apple Inc

Quick summary

Work type
On-site
Location
Cupertino, CA
Salary
$126,800–$190,900 / yr
Posted
52 days ago

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $159k
This role $159k
$117k most similar roles pay here $201k

This role pays more than 54% of similar roles. Most pay $124,750–$193,000 — the shaded band above. At the midpoint, this role pays about $159k versus about $159k for comparable roles.

Based on 239 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · STA Engineer

As an ASIC STA Engineer at Apple, you will join a dynamic team of problem solvers responsible for leading-edge IP development and coordinating with multiple SOC teams. Your day-to-day responsibilities include full chip and block level timing closure/constraints ownership throughout the project lifecycle, collaborating closely with specialists from SoC Design, Verification, DFT, Architecture, and Physical Design teams. You will work with CAD and Flow teams to define and improve front-end design methodologies, develop and maintain timing analysis methodology and flows, and ensure high-quality IP deliverables. The ideal candidate possesses strong digital design fundamentals, familiarity with ASIC design timing concepts, proficiency in scripting languages like TCL, Python, and Perl, and experience with STA tools such as Primetime. This role requires a self-starter attitude and the ability to communicate effectively across various internal groups.

What you'll do

  • Lead edge IP development and coordinate with multiple SOC teams.
  • Own full chip and block level timing closure/constraints throughout the project.
  • Work with CAD and Flow teams to define and improve front-end design methodologies.
  • Develop and maintain methodology and flows related to timing analysis.
  • Collaborate with specialists from SoC Design, Verification, DFT, Architecture, and Physical Design.

What we're looking for

  • Strong fundamentals in digital design and ASIC timing concepts.
  • Proficiency in scripting languages like TCL, Python, and Perl.
  • Experience with STA tools (Primetime) and writing timing constraints.
  • Knowledge of front-end design tools and methodologies including synthesis.
  • Self-motivated and able to communicate effectively across internal teams.

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