STA Engineer

Apple Inc

Confirmed live 2 days ago Low trust

Quick summary

Work type
On-site
Location
Cupertino, CA
Salary
$129,300–$194,700 / yr
Posted
144 days ago
Freshness
Confirmed live 2 days ago
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $158k
This role $162k
$119k most similar roles pay here $203k

This role pays more than 53% of similar roles. Most pay $129,243–$186,975 — the shaded band above. At the midpoint, this role pays about $162k versus about $158k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · STA Engineer

Role Posting Log in to save

STA Engineer will join the hardware team to lead edge IP development and coordinate with multiple SOC teams. The role involves executing design and integration tasks for high quality IP deliverables while taking ownership of full chip and block level timing closure and constraints throughout the entire project lifecycle. This position requires collaborating with SoC Design, Verification, DFT, Architecture, and Physical Design specialists, as well as working with CAD and Flow teams to define and improve front-end design methodologies. The engineer will develop and maintain methodology and flows related to timing analysis. Key technical requirements include strong digital design fundamentals, familiarity with ASIC design timing concepts, and proficiency in scripting languages like TCL, Python, and Perl. Experience with Primetime tools, writing timing constraints, and knowledge of synthesis or logic equivalence checks is also valued.

Skills

STA ASIC Design Timing Closure TCL Python Perl Primetime Synthesis Logic Equivalence Check Digital Design SOC Design

What you'll do

  • Own full chip and block level timing closure and constraints throughout the project lifecycle.
  • Execute design and integration tasks for high-quality IP deliverables across multiple SoC teams.
  • Develop and maintain methodologies and flows specifically related to timing analysis.
  • Collaborate with CAD and Flow teams to define and improve front-end design methodologies.
  • Write and manage timing constraints using industry-standard tools like Primetime.
  • Perform synthesis and logic equivalence checks as part of the front-end design process.
  • Coordinate with SoC Design, Verification, DFT, Architecture, and Physical Design teams.

What we're looking for

  • Bachelor's Degree is required.
  • Strong fundamentals in digital design are preferred.
  • Familiarity with ASIC design timing concepts is preferred.
  • Proficiency in scripting languages such as TCL, Python, and Perl is preferred.
  • Experience with STA tools like Primetime and knowledge of timing constraints and corners is a plus.
  • Familiarity with front-end tools and methodologies including Synthesis and Logic equivalence checks is preferred.
  • Ability to communicate effectively across all internal groups is required.

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