STA Engineer

Apple Inc

Confirmed live 2 days ago Low trust

Quick summary

Work type
On-site
Location
Cupertino, CA
Salary
$184,700–$324,800 / yr
Posted
144 days ago
Freshness
Confirmed live 2 days ago
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $158k
This role $255k
$104k most similar roles pay here $348k

This role pays more than 95% of similar roles. Most pay $129,243–$186,900 — the shaded band above. At the midpoint, this role pays about $255k versus about $158k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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View all roles at Apple Inc

At a glance

TL;DR · STA Engineer

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STA Engineer will join the hardware team to lead edge IP development and coordinate with multiple SOC teams. The role involves owning full chip and block level timing closure throughout the project lifecycle, developing and maintaining methodology and flows for timing verification, and generating block and full chip timing constraints. This position focuses on Apple SoC chips in deep sub-micron technologies targeted for high end mobile applications. Key responsibilities include resolving complex timing issues for major building blocks of complex SoCs while collaborating with multi-functional teams. Required skills include proficiency in scripting languages like TCL and Perl, along with knowledge of digital design fundamentals. Preferred experience includes using Primetime for STA, performing constraint analysis with Synopsys GCA, and addressing signal integrity issues across various timing corners and process variations.

Skills

STA ASIC Design Timing Closure TCL Perl Primetime Synthesis Logic Equivalence Check Synopsys GCA Constraint Analysis Signal Integrity Digital Design SOC Design

What you'll do

  • Own full chip and block level timing closure throughout the entire project lifecycle.
  • Develop and maintain methodologies and flows related to timing verification and closure.
  • Generate block and full chip timing constraints for high-end mobile SoC designs.
  • Resolve complex timing issues for major building blocks of complex SoCs.
  • Execute design and integration tasks for high-quality IP deliverables.
  • Perform constraint analysis and debug using industry standard tools.
  • Utilize scripting languages like TCL and Perl to support timing verification workflows.

What we're looking for

  • Bachelor's Degree is required.
  • 10 years of experience are required.
  • Strong fundamentals in digital design are preferred.
  • Proficiency in scripting languages such as TCL and Perl is preferred.
  • Familiarity with ASIC design timing concepts is preferred.
  • Experience with STA tools like Primetime is a plus.
  • Familiarity with front-end tools and methodologies like Synthesis and Logic equivalence checks is preferred.
  • Knowledge of timing corners, process variations, and signal integrity issues is a plus.

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