STA Engineer

Apple Inc

Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $181,100–$318,400 / yr
Posted: 52 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $159k

This role $250k

$102k most similar roles pay here $342k

This role pays more than 90% of similar roles. Most pay $124,750–$193,000 — the shaded band above. At the midpoint, this role pays about $250k versus about $159k for comparable roles.

Based on 239 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · STA Engineer

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As an ASIC STA Engineer at this leading technology company, you will play a critical role in the SOC design team by owning full chip and block level timing closure throughout the project lifecycle. Your responsibilities include developing and maintaining methodologies for timing verification and closure, generating constraints for both blocks and full chips, and collaborating with multi-functional teams to resolve complex timing issues in high-end mobile SoCs. You will work on cutting-edge Apple SoC chips using deep sub-micron technologies, requiring expertise in STA tools like Primetime, constraint analysis, and signal integrity issues. Familiarity with Synopsys GCA for constraint debugging is beneficial, as well as a strong understanding of timing corners/modes and process variations.

Skills

Primetime Synopsys GCA STA ASIC SOC design Timing verification Constraint analysis Docker Python CI/CD

What you'll do

Own full chip and block level timing closure throughout the project.
Develop and maintain methodology for timing verification and closure.
Generate block and full chip timing constraints.
Resolve complex timing issues in major SoC building blocks.
Work closely with multi-functional teams on timing challenges.

What we're looking for

At least 10 years of experience in SOC design or equivalent.
Expertise in full chip and block level timing closure throughout project lifecycle.
Development and maintenance of methodology for timing verification and closure.
Proficiency in generating block and full chip timing constraints.
Experience with STA tools like Synopsys Primetime is beneficial.
Knowledge of constraint analysis, debug using industry standard tools preferred.
Understanding of timing corners/modes, process variations, and signal integrity issues.

Remote

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