STA Engineer

Apple Inc

Quick summary

Work type: On-site
Location: Austin, TX
Posted: 52 days ago
Nearby: 99+ roles within 25 mi

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How this pay compares to similar roles

Similar $159k

$117k most similar roles pay here $201k

This listing doesn't post a salary. Most similar roles pay $124,750–$193,000.

Based on 239 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · STA Engineer

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As an ASIC STA Engineer at the senior level, you will join a dynamic team responsible for full chip and block-level timing closure throughout SOC design projects. Your daily tasks will include developing and maintaining methodologies for timing verification and closure, generating constraints for both blocks and full chips, and collaborating with multi-functional teams to resolve complex timing issues in high-end mobile SoCs. You should be proficient in STA tools like Primetime and familiar with constraint analysis using Synopsys GCA. Knowledge of timing corners/modes, process variations, and signal integrity is beneficial. This role requires strong communication skills to effectively interact across various internal groups on a large-scale project targeting deep sub-micron technologies for high-end mobile applications.

Skills

Primetime Synopsys Galaxy Constraint Analyzer STA ASIC SOC design timing verification constraint analysis Python Tcl Perl Unix/Linux CI/CD

What you'll do

Lead full chip and block level timing closure throughout the project lifecycle.
Develop and maintain methodologies for timing verification and closure processes.
Generate comprehensive timing constraints for both blocks and full chips.
Resolve complex timing issues in major building blocks of advanced SoCs.
Collaborate with multi-functional teams to ensure successful timing closure.
Analyze and debug constraint issues using industry-standard tools like Synopsys GCA.

What we're looking for

Minimum 10 years of experience in SOC design or equivalent.
Expertise in full chip and block level timing closure throughout project lifecycle.
Development and maintenance of methodology for timing verification and closure.
Proficiency in generating block and full chip timing constraints.
Experience with STA tools like Synopsys Primetime is beneficial.
Knowledge of constraint analysis, debug using industry standard tools preferred.
Understanding of timing corners/modes, process variations, and signal integrity issues.

Remote

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