STA Engineer

What you'll do

• Own full chip and block level timing closure throughout the entire project lifecycle.
• Develop and maintain methodologies and flows related to timing verification and closure.
• Generate block and full chip timing constraints for high-end mobile SoC designs.
• Resolve complex timing issues for major building blocks of complex SoCs.
• Coordinate with multiple SOC teams to execute design and integration tasks for high-quality IP deliverables.
• Perform constraint analysis and debug using industry standard tools.
• Utilize scripting languages like TCL and Perl to support timing verification workflows.

What we're looking for

• Bachelor's Degree is required.
• 10 years of experience are required.
• Strong fundamentals in digital design are required.
• Proficiency in scripting languages such as TCL and Perl is preferred.
• Familiarity with ASIC design timing concepts is preferred.
• Experience with STA tools like Primetime is a plus.
• Familiarity with front-end tools and methodologies like Synthesis and Logic equivalence checks is preferred.
• Knowledge of timing corners, process variations, and signal integrity issues is a plus.